MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 15

• Manufacturer Part Number: MT90401AB1
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB1

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

1.7
An internal state machine can be enabled to control the TIE Corrector Circuit as shown in Figure 1. In hardware
mode, control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). In
Microport mode, control is based on the state of control bits RSEL, MS1 and MS2 and the PCCi pin. When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
1.8
The MT90401 uses an external oscillator as the master timing source. For recommended master timing circuits,
see the Applications - Master Clock section.
2.0
The MT90401 has three possible modes of operation, Normal, Holdover and Freerun.
In hardware mode the Mode/Control Select pins MS2 and MS1 select the mode and method of control as shown in
Table 3.
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and
Figure 12 for details of the state change sequences.
State Machine Control
Master Clock
Control and Mode of Operation
Figure 6 - Control State Machine Block Diagram
RSEL
Table 3 - Operating Modes and States
Table 2 - Input Reference Selection
MS2
RSEL
Select MUX
0
0
1
1
Reference
0
1
To
MS1
Zarlink Semiconductor Inc.
0
1
0
1
MS1
MT90401
State Machine
Corrector
Input Reference
To TIE
Control
Enable
15
HOLDOVER
FREERUN
SEC
MS2
NORMAL
Reserved
PRI
Mode
To DPLL
Select
State
PCCi
Data Sheet