MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 21
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MT90401AB1
Manufacturer Part Number
MT90401AB1
Description
Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
Manufacturer
Zarlink
Datasheet
1.MT90401AB.pdf
(38 pages)
Specifications of MT90401AB1
Package
80LQFP EP
Number Of Transceivers
1
Standard Framing Format
SDH|SONET
Maximum Supply Current
150 mA
Minimum Single Supply Voltage
3 V
Maximum Single Supply Voltage
3.6 V
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT90401AB1
Manufacturer:
st
Quantity:
421
3.4
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT90401, the Freerun accuracy is equal to the
Master Clock (C20i) accuracy.
3.5
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the MT90401, the storage value is determined
while the device is in Normal Mode and locked to an external reference signal. The initial frequency offset of the
MT90401 in Holdover Mode is +20 x 10
requirements of +50 x 10
determined by the stability of the 20 MHz Master Clock Oscillator.
The absolute Master Clock (C20i) accuracy of the MT90401 does not affect Holdover accuracy, but the change in
C20i accuracy while in Holdover Mode does.
NOTES:
(XXX)
{A}
Movement to Normal State from any state requires a valid input signal
Frequency Accuracy
Holdover Accuracy
Phase Re-Alignment
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
MS2 MS1 RSEL
Invalid Reference Signal
Primary
Normal
(000)
S1
(PCCi=0)
(PCCi=1)
-9
PCCi-0
PCCi-1
. Once the MT90401 has transitioned into Holdover Mode, holdover stability is
{A
Auto-Holdover
Holdover
Primary
Primary
(010)
S1A
S1H
Figure 12 - Control State Diagram
-9
. This is more accurate than Telcordia’s GR-1244-CORE stratum 3
Zarlink Semiconductor Inc.
MT90401
Freerun
21
(10X)
S0
In the case where 19.44 MHz input reference clocks are
selected (FS2,FS1 = 00) the MT90401 may latch
inaccurate phase reading during transition between
states: S1A>>S1 and S2A>>S2 which may cause
frequency step exceeding ±4.6 ppm and longer than 100
sec lock time.
Auto-Holdover
Secondary
Secondary
Holdover
(011)
S2A
S2H
{A}
Secondary
Normal
(001)
S2
Data Sheet