MT90401AB1 Zarlink, MT90401AB1 Datasheet - Page 27

• Manufacturer Part Number: MT90401AB1
• Description: Framer SDH/SONET 3.3V 80-Pin LQFP EP Tray
• Manufacturer: Zarlink

Specifications of MT90401AB1

• Package: 80LQFP EP
• Number Of Transceivers: 1
• Standard Framing Format: SDH|SONET
• Maximum Supply Current: 150 mA
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V

Bit
0
1-0
5-0
Bit
Bit
7
6
7
6
5
4
3
2
Name
TCLR
HOLDOVER
E3DS3/OC3
SECOOR
PRIOOR
E3/DS3
Name
LOCK
Name
FLim
RSV
RSV
RSV
Table 6 - Control Register 1 (Address 00H - Read/Write) (continued)
TIE Clear. Set to zero to clear the Time Interval Error correction circuit resulting in a
realignment of output phase with input phase. When this bit is zero, the Time Interval
Error correction circuit is disabled. When this bit is one, the Time Interval Error correction
circuit will function normally.
Table 8 - Control Register 2 (Address 04H - Read/Write)
Table 7 - Status Register 1 (Address 01H - Read Only)
Primary Out Of Range. A one indicates that the primary reference is off the PLL
center frequency by more than 12 ppm. The measurement is done on a 1 second
basis using a signal derived from the 20 MHz clock input on C20i. When the
accuracy of the 20 MHz clock is
PRIOOR signal will be
Secondary Out of Range. A one indicates that the secondary reference is off the
PLL center frequency by more than 12 ppm. The measurement is done on a 1
second basis using a signal derived from the 20 MHz clock input on C20i. When the
accuracy of the 20 MHz clock is
PRIOOR signal will be
Lock. This bit goes high when the PLL is in frequency lock to the input reference.
Holdover. This bit goes high whenever the device is in Holdover mode.
Reserved.
Frequency Limit. This bit goes high whenever the reference frequency hits the
input frequency offset tolerance of the PLL. This bit can flicker high in the event of
large excursions of still tolerable input jitter.
Reserved.
E3DS3/OC3 Selection. Set this bit to zero to enable the differential 155.52 MHz
output clock on the C155N/C155P pins and cause the C34/C44 pin to output its
nominal clock frequency divided by 4. Set this bit to one to disable the differential
155.52 MHz output clock on the C155N/C155P pins and cause the C34/C44 pin to
output its nominal clock frequency.
E3/DS3. Set this bit low to select a clock rate of 44.736 MHz for the C34/C44 pin.
Set high to select a clock rate of 34.368 MHz for the C34/C44 pins.
Reserved. Set to zero for normal operation.
Zarlink Semiconductor Inc.
MT90401
+
+
16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm.
27
Functional Description
Functional Description
Functional Description
±
±
4.6 ppm, the effective out of range limits of the
4.6ppm, the effective out of range limits of the
Data Sheet