DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 103
DS21Q55N
Manufacturer Part Number
DS21Q55N
Description
Framer E1/J1/T1 3.3V 256-Pin BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21Q55N.pdf
(237 pages)
Specifications of DS21Q55N
Package
256BGA
Number Of Transceivers
4
Standard Framing Format
E1|J1|T1
Maximum Supply Current
75(Typ) mA
Minimum Single Supply Voltage
3.135 V
Maximum Single Supply Voltage
3.465 V
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The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1
channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel
code array.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 1 to 8 Code Insertion Control Bits (CH1 to CH8)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 9 to 16 Code Insertion Control Bits (CH9 to CH16)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Transmit Channels 25 to 32 Code Insertion Control Bits (CH25 to CH32)
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle-code array into the transmit data stream
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle code-array into the transmit data stream
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle code-array into the transmit data stream
0 = do not insert data from the idle-code array into the transmit data stream
1 = insert data from the idle-code array into the transmit data stream
CH16
CH24
CH32
CH8
7
0
7
0
7
0
7
0
CH15
CH23
CH31
CH7
TCICE1
Transmit-Channel Idle-Code Enable Register 1
80h
TCICE2
Transmit-Channel Idle-Code Enable Register 2
81h
TCICE3
Transmit-Channel Idle-Code Enable Register 3
82h
TCICE4
Transmit-Channel Idle-Code Enable Register 4
83h
6
0
6
0
6
0
6
0
CH14
CH22
CH30
CH6
5
0
5
0
5
0
5
0
CH13
CH21
CH29
CH5
4
0
4
0
4
0
4
0
103 of 237
CH12
CH20
CH28
CH4
0
0
0
0
3
3
3
3
CH11
CH19
CH27
CH3
2
0
2
0
2
0
2
0
CH10
CH18
CH26
CH2
1
0
1
0
1
0
1
0
CH17
CH25
CH1
CH9
0
0
0
0
0
0
0
0
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