X28HC64SI-12 Intersil, X28HC64SI-12 Datasheet
X28HC64SI-12
Specifications of X28HC64SI-12
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X28HC64SI-12 Summary of contents
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... All other trademarks mentioned are the property of their respective owners. X28HC64 64K Bit June 7, 2006 FN8109.1 TSOP X28HC64 PGA I/O I/O I/O I I/O I X28HC64 (BOTTOM VIEW Bottom View | Intersil (and design registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved ...
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... X28HC64EM-70 X28HC64J-70 X28HC64J-70* X28HC64JI-70 X28HC64JI-70* X28HC64JI-70 Z X28HC64JIZ-70* (Note) X28HC64J-70 Z X28HC64JZ-70* (Note) X28HC64KM-70 X28HC64KM-70 X28HC64P-70 X28HC64P-70 X28HC64P-70 Z X28HC64PZ-70 (Note) X28HC64S-70 X28HC64S-70* X28HC64SI-70 X28HC64SI-70* X28HC64SM-70 X28HC64SM-70* X28HC64S-70 Z X28HC64SZ-70 (Note) X28HC64J-90 X28HC64J-90* X28HC64JI-90 X28HC64JI-90* X28HC64JI-90 Z X28HC64JIZ-90* (Note) X28HC64KM-90 X28HC64KM-90 C X28HC64KMB-90 X28HC64KMB-90 X28HC64P-90 X28HC64P-90 X28HC64PI-90 ...
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... X28HC64JZ-12* (Note) X28HC64J-12 Z X28HC64KMB-12 C X28HC64KMB-12 X28HC64P-12 X28HC64P-12 X28HC64PI-12 X28HC64PI-12 X28HC64PIZ-12 (Note) X28HC64PI-12 Z X28HC64PZ-12 (Note) X28HC64P-12 Z X28HC64S-12* X28HC64S-12 X28HC64SI-12* X28HC64SI-12 X28HC64SIZ-12* (Note) X28HC64SI-12 Z X28HC64SZ-12 (Note) X28HC64S-12 Z X28HC64DM-15 X28HC64DM-15 X28HC64J-15T1 X28HC64J-15 X28HC64JI-15 X28HC64JI-15 X28HC64JM-15 X28HC64JM-15 X28HC64JZ-15* (Note) X28HC64J-15 Z X28HC64KMB-15 C X28HC64KMB-15 X28HC64P-15 X28HC64P-15 X28HC64PIZ-15 (Note) ...
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... Y Buffers Latches and Decoder CE Control OE Logic and Timing Symbol Description A -A Address Inputs 0 12 I/O -I/O Data Input/Output Write Enable CE Chip Enable OE Output Enable V + Ground Connect 65,536-Bit EEPROM Array I/O Buffers and Latches I/O –I Data Inputs/Outputs FN8109.1 June 7, 2006 ...
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DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus ...
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DATA POLLING I/O 7 Figure 2. DATA Polling Bus Sequence Last Write I – Figure 3. DATA Polling Software Flow Write Data Writes Complete? Yes Save Last Data and ...
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THE TOGGLE BIT I/O 6 Figure 4. Toggle Bit Bus Sequence Last WE Write Beginning and ending state of I/O Figure 5. Toggle Bit Software Flow Last Write Yes Load Accum From Addr N ...
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... SOFTWARE DATA PROTECTION The X28HC64 offers a software controlled data protec- tion feature. The X28HC64 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/- down operations through the use of external circuits ...
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SOFTWARE DATA PROTECTION Figure 6. Timing Sequence—Byte or Page Write Data AAA ADDR 1555 CE WE Figure 7. Write Sequence for Software Data Protection Write Data AA to Address 1555 Write Data 55 to Address 0AAA Write ...
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... In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algo- rithm will reset the internal protection circuit. After t the X28HC64 will be in standard operating mode. Note: Once initiated, the sequence of write operations should not be interrupted ...
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SYSTEM CONSIDERATIONS Because the X28HC64 is frequently used in large memory arrays provided with a two-line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipa- tion, and eliminate the possibility ...
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ABSOLUTE MAXIMUM RATINGS Temperature under bias X28HC64 ......................................... -10°C to +85°C X28HC64I, X28HC64M .................. -65°C to +135°C Storage temperature.......................... -65°C to +150°C Voltage on any pin with respect to V ......................................... -1V to +7V SS D.C. output current ............................................... 5mA ...
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ENDURANCE AND DATA RETENTION Parameter Minimum endurance Data retention POWER-UP TIMING Symbol (3) t Power-up to read operation PUR (3) t Power-up to write operation PUW CAPACITANCE T = +25° 1MHz Symbol Parameter (3) C Input/output ...
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A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Read Cycle Limits Symbol Parameter t Read cycle time RC t Chip enable access time CE t Address access time AA t Output enable access time OE ( ...
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WRITE CYCLE LIMITS Symbol Parameter (5) t Write cycle time WC t Address setup time AS t Address hold time AH t Write setup time CS t Write hold time pulse width High setup ...
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CE CONTROLLED WRITE CYCLE Address OES Data In Data Out Page Write Cycle ( (8) Address* I/O Byte 0 *For each successive write within the page write ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...