P80C32X2BBD NXP Semiconductors, P80C32X2BBD Datasheet - Page 39

• Manufacturer Part Number: P80C32X2BBD
• Description: MCU 8-Bit 80C 80C51 CISC ROMLess 5V 44-Pin LQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P80C32X2BBD

• Package: 44LQFP
• Device Core: 80C51
• Family Name: 80C
• Maximum Speed: 33 MHz
• Ram Size: 256 Byte
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: ROMLess
• Number Of Programmable I/os: 32
• Interface Type: UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

Philips Semiconductors
DC ELECTRICAL CHARACTERISTICS
T
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
3. Capacitive loading on ports 0 and 2 may cause the V
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
5. See Figures 36 through 39 for I
6. This value applies to T
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, I
9. ALE is tested to V
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
2003 Jan 24
amb
SYMBOL PARAMETER
V
V
V
V
V
V
V
I
I
I
I
V
R
C
IL
TL
LI
CC
IL
IH
IH1
OL
OL1
OH
OH1
RAM
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),
low power, high speed (30/33 MHz)
RST
IO
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
address bits are stabilizing.
maximum value when V
12-clock mode characteristics:
If I
test conditions.
(except EA is 25 pF).
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
= 0 C to +70 C or –40 C to +85 C; V
OL
Active mode (operating):
Active mode (reset):
Idle mode:
Maximum I
Maximum I
Maximum total I
exceeds the test condition, V
Input low voltage
Input high voltage (ports 0, 1, 2, 3, EA)
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3
Output low voltage, port 0, ALE, PSEN
Output high voltage, ports 1, 2, 3
Output high voltage (port 0 in external bus
mode), ALE
Logical 0 input current, ports 1, 2, 3
Logical 1-to-0 transition current, ports 1, 2, 3
Input leakage current, port 0
Power supply current (see Figure 34):
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped
(see Figure 39 for conditions)
RAM keep-alive voltage
Internal reset pull-down resistor
Pin capacitance
OL
OL
per port pin:
per 8-bit port:
OH1
OL
9
, except when ALE is off then V
amb
for all outputs:
, PSEN
IN
10
is approximately 2 V.
11
= 0 C to +70 C. For T
(except EA)
3
I
I
I
CC(MAX)
CC(MAX)
CC(MAX)
CC
test conditions and Figure 34 for I
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
= 1.0 mA + 0.9 mA
= 7.0 mA + 0.5 mA x FREQ.[MHz]
= 1.0 mA + 0.18 mA
15 mA (*NOTE: This is 85 C specification.)
26 mA
71 mA
11
CC
8
3
= 5 V 10%; V
OL
amb
7, 8
must be externally limited as follows:
= –40 C to +85 C, I
OH
OH
6
on ALE and PSEN to momentarily fall below the V
is the voltage specification.
TEST
CONDITIONS
4.5 V < V
–
–
V
V
V
V
V
V
0.45 < V
T
T
–
–
–
amb
amb
CC
CC
CC
CC
IN
IN
SS
FREQ.[MHz]
= 0.4 V
= 2.0 V; See note 4
= 4.5 V; I
= 4.5 V; I
= 4.5 V; I
= 4.5 V; I
FREQ.[MHz]
= 0 C to 70 C
= –40 C to +85 C
= 0 V (30/33 MHz max. CPU clock)
IN
CC
39
< V
CC
< 5.5 V
OL
OL
OH
OH
vs. Frequency.
CC
TL
= 1.6 mA
= 3.2 mA
= –30 A
= –3.2 mA
– 0.3
= –750
2
2
.
LIMITS
MIN
–0.5
0.2 V
0.7 V
–
–
V
V
–1
–
–
1.2
40
–
CC
CC
OL
OL
– 0.7
– 0.7
CC
CC
s of ALE and ports 1 and 3. The noise is due
can exceed these conditions provided that no
+0.9
P80C3xX2; P80C5xX2;
TYP
2
3
CC
1
–0.7 specification when the
MAX
0.2 V
V
V
0.4
0.4
–
–
–50
–650
30
50
225
15
10
CC
CC
+0.5
+0.5
CC
P87C5xX2
–0.1
Product data
UNIT
V
V
V
V
V
V
V
V
k
pF
A
A
A
A
A