MT90869AG Zarlink, MT90869AG Datasheet - Page 59
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MT90869AG
Manufacturer Part Number
MT90869AG
Description
Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.MT90869AG.pdf
(84 pages)
Specifications of MT90869AG
Package
272BGA
Number Of Ports
64
Fabric Size
16K x 16K|8K x 8K
Switch Core
Non-Blocking|Blocking
Port Speed
8.192|4.096|2.048 Mbps
Operating Supply Voltage
1.8|3.3 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT90869AG
Manufacturer:
ZARLINK
Quantity:
2 388
Company:
Part Number:
MT90869AG2
Manufacturer:
ZARLINK
Quantity:
96
13.7
Address 0063h to 0082h
Thirty-two backplane input delay registers (BIDR0 to BIDR31) allow users to program the input bit delay for the
backplane input data streams BSTi0-31. The possible adjustment is 7 3/4 of the data rate, in steps of 1/4 of the
data rate. The data rate can be either 2 Mb/s, 4 Mb/s, 8 Mb/s, 16 Mb/s, or 32 Mb/s.
The BIDR0 to BIDR31 registers are configured as follows:
13.7.1
These five bits define how long in the cycle the serial interface receiver takes to recognize and stores the bit 0 from
the BSTi input pins: i.e., start assuming a new frame. Input bit delay adjustment can range up to 7
forward with resolution of
This can be described as BIDn(4:0) = (number of bits delay) / 4
For example, if BID(4:0) is set to 10011 (19), the input bit delay = 19 *
Table 26 illustrates the bit delay selection.
Mode, n = 0 to15 for 32 Mb/s Mode)
(where n = 0 to 31 for Non-32 Mb/s
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Backplane Input Delay Bits 4-0 (BID4 - BID0)
BIDRn Bit
15-5
4-0
0 (Default)
Data Rate
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
1/4
1/2
3/4
Table 25 - Backplane Input Bit Delay Register (BIDRn) Bits
1
2
3
1
Table 26 - Backplane Input Bit Delay Programming Table
/
4
bit period.
BID4
Reserved
BID(4:0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Zarlink Semiconductor Inc.
BID3
MT90869
Corresponding Delay Bits
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Reset
0
0
59
Reserved
Backplane Input Bit Delay Register
The binary value of these bits refers to the input bit
delay value for the backplane input stream
BID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
/
4
= 4
BID1
3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
/
4.
Description
BID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Data Sheet
3
/
4
bit periods