MT90869AG Zarlink, MT90869AG Datasheet - Page 80

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Backplane and Local Output High-Impedance Timing
Note 1: High Impedance is measured by pulling to mid-rail with R
LSTo0 - 31
2.048 Mb/s
4.096 Mb/s
LSTo0 - 31
4.096 Mb/s
1
2
8.192 Mb/s
* CK_int is the internal clock signal of 131.072 MHz
8.192 Mb/s
LSTo0 - 31
LSTi0 - 31
2.048 Mb/s
LSTi0 - 31
LSTi0 - 31
CK_int *
STo delay - Active to High-Z
Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to High-Impedance
FP8i
C8i
Characteristic
Bit0
Ch31
Ch127
Bit1
- High-Z to Active
Figure 27 - ST-BUS Local Data Timing Diagram (8 Mb/s, 4 Mb/s, 2 Mb/s)
1
Ch31
Bit0
Ch63
Bit0
Ch127
Ch63
Bit0
Bit0
0
t
Ch0
LFBOS
Bit7
t
t
LSOD8
LIDS4
t
7
LSOD4
Sym.
t
t
t
LSOD2
ODE
ODZ
t
t
Ch0
Bit7
DZ
ZD
t
t
LSIS8
LIDS8
t
LSIH8
Bit7
Ch0
t
LIDS2
Zarlink Semiconductor Inc.
Ch0
Bit6
6
Min.
MT90869
t
LSIS4
t
LSIH4
Ch0
Bit7
L
80
Ch0
Bit5
Typ.
= 1k//1k potential divider, with timing corrected for C
5
Bit7
Ch0
Ch0
Bit6
Max.
Ch0
Bit6
t
15
14
LSIS2
4
4
Bit4
Ch0
4
t
LSIH2
Unit
ns
ns
ns
ns
s
Bit3
Ch0
3
Ch0
R
R
R
Bit5
L
L
L
Ch0
Bit5
=1K, C
=1K, C
=1K, C
Bit2
Ch0
Test Conditions
2
L
L
L
Ch0
Bit6
=50pF, See Note 1
=50pF, See Note 1
=50pF, See Note 1
Bit1
Ch0
1
Ch0
Bit6
Data Sheet
L
Ch0
Bit4
.
Bit4
Ch0