LFX200EB-03FN256I Lattice, LFX200EB-03FN256I Datasheet - Page 7

• Manufacturer Part Number: LFX200EB-03FN256I
• Description: IC FPGA 210KGATES 256FPBGA
• Manufacturer: Lattice

Specifications of LFX200EB-03FN256I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 4. LUT in Shift Register Mode
Carry Chain Generator
The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a two-
input XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the
carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0. The sum
output of the CCG can be fed to the CSE through the WLG. The carryout must propagate to CLE0 for use outside
the PFU. The carryout from the PFU can feed the W0 input of CSE0. The CCG also helps to effectively implement
wider functions by using its logic elements to expand the capabilities of the LUT-4.
Figure 5. Carry Chain Generator
Wide Logic Generator
The WLG contains the logic necessary to implement wide gate functions. This is made up of a set of multiplexers
that are located between the CLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU.
The outputs of each CLE can be cascaded in the WLG to build wide gating functions. Wide multiplexing functions
are also possible with a similar use of the WLG. Figure 6 illustrates the WLG.
CIN
B
A
SEL (SHIFTIN)
PFUCLK0
CEB0
LUT-4
7
COUT
SUM
SHIFTOUT (4A)
CIN from
Routing
COUT(r,c)
CLE0
CLE1
CLE3
ispXPGA Family Data Sheet
CLE2
COUT(r+1,c)
COUT to
SUM3
SUM2
SUM1
SUM0
CSE0