ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet - Page 15

• Manufacturer Part Number: ISL23328TFVZ-TK
• Description: IC DGTL POT 2CH 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23328TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
The ISL23328 supports an I
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the device
being controlled is the slave. The master always initiates data
transfers and provides the clock for both transmit and receive
operations. Therefore, the ISL23328 operates as a slave device
in all applications.
All communication over the I
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 27). On
power-up of the ISL23328, the SDA pin is in the input mode.
All I
which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The
2
0
C Serial Interface
2
C interface operations must begin with a START condition,
POWER-UP
SHDN ACTIVATED SHDN RELEASED
FIGURE 26. SHUTDOWN MODE WIPER RESPONSE
USER PROGRAMMED
SCL
SDA
MID SCALE = 40H
SHDN MODE
2
2
C bidirectional bus oriented
C interface is conducted by sending
15
START
TIME (s)
FIGURE 27. VALID DATA CHANGES, START AND STOP CONDITIONS
AFTER SHDN
WIPER RESTORE TO
THE ORIGINAL POSITION
STABLE
ISL23328
DATA
CHANGE
DATA
ISL23328 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 27). A START condition is ignored
during the power-up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 27). A STOP condition at the end of a read
operation or at the end of a write operation places the device in
its standby mode.
An ACK (Acknowledge) is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data
(see Figure 28).
The ISL23328 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of an Address Byte. The ISL23328 also
responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
A valid Identification Byte contains 1010 as the four MSBs, and
the following three bits are matching the logic values present at
pins A2, A1 and A0. The LSB is the Read/Write bit. Its value is “1”
for a Read operation and “0” for a Write operation (see Table 3).
(MSB)
2
1
C interface operations must be terminated by a STOP
STABLE
LOGIC VALUES AT PINS A2, A1 AND A0 RESPECTIVELY
DATA
0
TABLE 3. IDENTIFICATION BYTE FORMAT
1
0
STOP
A2
A1
A0
August 19, 2011
(LSB)
FN7902.0
R/W