ISL23328TFVZ-TK Intersil, ISL23328TFVZ-TK Datasheet - Page 16

• Manufacturer Part Number: ISL23328TFVZ-TK
• Description: IC DGTL POT 2CH 100K 14TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23328TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 2
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: I²C (Device Address)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL23328 responds
with an ACK. The data is transferred from I
corresponding register at the 9th clock of the data byte and the
device enters its standby state (see Figures 28 and 29).
It is possible to perform a sequential Write to all DCP channels
via a single Write operation. The command is initiated by sending
an additional Data Byte after the first Data byte instead of
sending a STOP condition.
SIGNAL AT SDA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SDA OUTPUT FROM
SDA OUTPUT FROM
THE SLAVE
TRANSMITTER
S
A
R
T
T
SCL FROM
RECEIVER
MASTER
1
IDENTIFICATION
0
BYTE WITH
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
1
R/W = 0
THE MASTER
0
THE SLAVE
A2
16
A1
START
A0
0
A
C
K
FIGURE 28. ACKNOWLEDGE RESPONSE FROM RECEIVER
0 0 0
HIGH IMPEDANCE
2
C block to the
ADDRESS
S
A
R
T
T
BYTE
1
IDENTIFICATION
FIGURE 29. BYTE WRITE SEQUENCE
0
1
FIGURE 30. READ SEQUENCE
1
BYTE
0
A2
ISL23328
A1
A
C
K
A0
A
R
S
T
T
0
WRITE
1 0 1 0
IDENTIFICATION
A
C
K
BYTE WITH
R/W = 1
0 0 0
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 30). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL23328 responds
with an ACK; then the ISL23328 transmits Data Byte. The master
terminates the read operation issuing a NACK (ACK) and a STOP
condition following the last bit of the last Data Byte (see
Figure 30).
ADDRESS
A2
BYTE
A1
A0
1
READ
A
C
K
A
C
K
8
FIRST READ
DATA BYTE
DATA
BYTE
A
C
K
HIGH IMPEDANCE
ACK
9
A
C
K
A
C
K
S
T
O
P
LAST READ
DATA BYTE
August 19, 2011
FN7902.0
A
C
K
S
T
O
P