ISL23448TFVZ-TK Intersil, ISL23448TFVZ-TK Datasheet

ISL23448TFVZ-TK

Manufacturer Part Number

ISL23448TFVZ-TK

Description

IC DGTL POT 4CH 100K 20TSSOP

Manufacturer

Intersil

Series

XDCP™r

Datasheet

1.ISL23448TFRZ-TK.pdf (21 pages)

Specifications of ISL23448TFVZ-TK

Taps

128

Resistance (ohms)

100K

Number Of Circuits

Temperature Coefficient

45 ppm/°C Typical

Memory Type

Volatile

Interface

4-Wire SPI (Chip Select)

Voltage - Supply

1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V

Operating Temperature

-40°C ~ 125°C

Mounting Type

Package / Case

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Current page: 1 of 21
Download datasheet (749Kb)

Quad, 128 Tap, Low Voltage Digitally Controlled

Potentiometer (XDCP™)

ISL23448

The ISL23448 is a volatile, low voltage, low noise, low power,

128 tap, quad digitally controlled potentiometer (DCP) with an

SPI Bus™ interface. It integrates four DCP cores, wiper

switches and control logic on a monolithic CMOS integrated

circuit.

Each digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

SPI bus interface. Each potentiometer has an associated

volatile Wiper Register (WRi, i = 0, 1, 2, 3) that can be directly

written to and read by the user. The contents of the WRi

controls the position of the wiper. When powered on, the wiper

of each DCP will always commence at mid-scale (64 tap

position).

The low voltage, low power consumption, and small package

of the ISL23448 make it an ideal choice for use in battery

operated equipment. In addition, the ISL23448 has a V

pin allowing down to 1.2V bus operation, independent from the

directly to the ISL23448 without passing through a voltage

level shifter.

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal processing.

Applications

• Power supply margining

• Trimming sensor circuits

• Gain adjustment in battery powered instruments

• RF power amplifier bias compensation

August 19, 2011

FN7905.0

10000

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

8000

6000

4000

2000

value. This allows for low logic levels to be connected

POSITION, 10kΩ DCP

TAP POSITION (DECIMAL)

LOGIC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.

128

1-888-INTERSIL or 1-888-468-3774

Features

• Four potentiometers per package

• 128 resistor taps

• 10kΩ, 50kΩ or 100kΩ total resistance

• SPI serial interface

• Power supply

• Maximum supply current without serial bus activity

• Shutdown Mode

• Wiper resistance: 70Ω typical @ V

• Power-on preset to mid-scale (64 tap position)

• Extended industrial temperature range: -40

• 20 Ld TSSOP or 20 Ld QFN packages

• Pb-free (RoHS compliant)

ISL23448

- No additional level translator for low bus supply

- Daisy Chaining of multiple DCPs

- V

(standby)

- 5µA @ V

- 2µA @ V

- Forces the DCP into an end-to-end open circuit and RWi is

- Reduces power consumption by disconnecting the DCP

1 DCP

connected to RLi internally

resistor from the circuit

All other trademarks mentioned are the property of their respective owners

LOGIC

= 1.7V to 5.5V analog power supply

= 1.2V to 5.5V SPI bus/logic power supply

REF

RH1

RL1

FIGURE 2. V

and V

RW1

LOGIC

= 5V

= 1.7V

REF

ISL28114

ADJUSTMENT

= 3.3V

C to +125

REF_M

Related parts for ISL23448TFVZ-TK

ISL23448TFVZ-TK Summary of contents

Page 1

... FIGURE 2. V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners = 5V LOGIC = 1.7V LOGIC = 3 ...

Page 2

Block Diagram V LOGIC SDI SDO I/O SCK BLOCK CS Pin Configurations ISL23448 (20 LD TSSOP) TOP VIEW 1 RL0 RW0 RH0 4 RL1 5 RW1 6 RH1 7 GND LOGIC SDI 10 ...

Page 3

... Ordering Information PART NUMBER (Notes PART MARKING ISL23448TFVZ 23448 TFVZ ISL23448UFVZ 23448 UFVZ ISL23448WFVZ 23448 WFVZ ISL23448TFRZ 448T ISL23448UFRZ 448U ISL23448WFRZ 448W NOTES: 1. Add “-TK” suffix for 1k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to 2 ...

Page 4

... Thermal Resistance (Typical TSSOP Package (Notes QFN Package (Notes Maximum Junction Temperature (Plastic Package .+150°C Storage Temperature Range .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C V Supply Voltage 1. Supply Voltage ...

Page 5

Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER VOLTAGE DIVIDER MODE ( RH; measured at RW, unloaded) CC INL Integral Non-linearity, Guaranteed ...

Page 6

Analog Specifications V = 2.7V to 5.5V Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER R Offset, wiper at 0 position offset (Note 16) Rmatch DCP to DCP Matching (Note 23) TCR Resistance ...

Page 7

Operating Specifications Boldface limits apply over the operating temperature range, -40°C to +125°C. SYMBOL PARAMETER t Wiper Response Time DCP tShdnRec DCP Recall Time From Shutdown Mode Ramp Rate (Note 21) CC, LOGIC CC , LOGIC ...

Page 8

Serial Interface Specification SYMBOL PARAMETER t SDO Output Fall Time Deselect Time CS NOTES: 8. Typical values are for T = +25°C and 3.3V supply voltages LSB = [V(RW) – V(RW) ]/127. V(RW) 127 0 ...

Page 9

Timing Diagrams Input Timing CS t LEAD SCK MSB SDI SDO Output Timing CS SCK t SO MSB SDO ADDR SDI XDCP™ Timing (For All Load Instructions) CS SCK MSB SDI V W SDO 9 ISL23448 t ...

Page 10

Typical Performance Curves 0.12 0.06 0.00 -0.06 -0. TAP POSITION (DECIMAL) FIGURE 3. 10kΩ DNL vs TAP POSITION, V 0.16 0.08 0.00 -0.08 -0. TAP POSITION (DECIMAL) FIGURE 5. 10kΩ INL vs TAP POSITION, ...

Page 11

Typical Performance Curves 0.4 0.3 0.2 0.1 0 TAP POSITION (DECIMAL) FIGURE 9. 10kΩ RINL vs TAP POSITION, V 100 +25° -40° TAP POSITION (DECIMAL) FIGURE 11. 10kΩ WIPER ...

Page 12

Typical Performance Curves 400 300 200 100 TAP POSITION (DECIMAL) FIGURE 15. 10kΩ TCr vs TAP POSITION TAP POSITION (DECIMAL) FIGURE 17. 100kΩ TCv vs TAP POSITION, V ...

Page 13

Typical Performance Curves 1V/DIV 0.2µs/DIV FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME CH1: RH TERMINAL CH2: RW TERMINAL 0.5V/DIV, 0.2µs/DIV -3dB FREQUENCY = 1.437MHz AT MIDDLE TAP FIGURE 23. 10kΩ -3dB CUT OFF FREQUENCY Functional Pin Descriptions Potentiometers Pins RH ...

Page 14

SERIAL DATA OUTPUT (SDO) The SDO is a serial data output pin. During a read cycle, the data bits are shifted out on the falling edge of the serial clock SCK and will be available to the master on the ...

Page 15

When the device enters shutdown, all current DCP WR settings are maintained. When the device exits shutdown, the wipers will return to the previous WR settings after a short settling time (see Figure 26). In shutdown mode, if there is ...

Page 16

SCK WR INSTRUCTION SDI SDO 1 CS SCK RD ADDR SDI SDO Applications Information Communicating with ISL23448 Communication with ISL23448 proceeds using SPI interface through the ACR (address 10000b), WR0 (addresses 00000b), WR1 (addresses 00001b), WR2 (addresses ...

Page 17

Wiper Transition When stepping up through each tap in voltage divider mode, some tap transition points can result in noticeable voltage transients, or overshoot/undershoot, resulting from the sudden transition from a very low impedance “make” much higher impedance ...

Page 18

SCK SDI INSTRUCTION SDO CS SCK 16 CLKS 16 CLKS SDI RD DCP2 RD DCP1 SDO FIGURE 32. DAISY CHAIN READ SEQUENCE DCP 18 ISL23448 ...

Page 19

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...

Page 20

Package Outline Drawing M20.173 20 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 2, 5/10 1 6.50 ±0.10 20 6.40 4.40 ±0. 0. TOP VIEW H C SEATING PLANE 0.10 C SIDE VIEW (5.65) ...

Page 21

Package Outline Drawing L20.3x4 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10 3. PIN 1 INDEX AREA A TOP VIEW (2.65) (3.80) (1.65) (2.80) TYPICAL RECOMMENDED LAND PATTERN 21 ISL23448 A B 20X 4 4.00 0.15 ...

Related keywords

ISL23448TFVZ-TK datasheet
ISL23448TFVZ-TK data sheet
ISL23448TFVZ-TK pdf datasheet
ISL23448TFVZ-TK component
ISL23448TFVZ-TK part
ISL23448TFVZ-TK distributor
ISL23448TFVZ-TK RoHS
ISL23448TFVZ-TK datasheet download