ISL23448TFVZ-TK Intersil, ISL23448TFVZ-TK Datasheet - Page 17

• Manufacturer Part Number: ISL23448TFVZ-TK
• Description: IC DGTL POT 4CH 100K 20TSSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL23448TFVZ-TK

• Taps: 128
• Resistance (ohms): 100K
• Number Of Circuits: 4
• Temperature Coefficient: 45 ppm/°C Typical
• Memory Type: Volatile
• Interface: 4-Wire SPI (Chip Select)
• Voltage - Supply: 1.2 V ~ 5.5 V, 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1µs). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,...,
6Fh to 7Fh, which have higher transient glitch. Note, that all
switching transients will settle well within the settling time as
stated in the datasheet. A small capacitor can be added
externally to reduce the amplitude of these voltage transients,
but that will also reduce the useful bandwidth of the circuit, thus,
this may not be a good solution for some applications. It may be
a good idea, in this case, to use fast amplifiers in a signal chain
for fast recovery.
µC
SDO 0
SDO 1
SDO 2
MOSI
MISO
SCK
SCK
SDI
CS
CS
17
CS
SCK
SDI
WR
DCP0
FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP
16 CLKLS
SDO
D C P2
FIGURE 29. DAISY CHAIN CONFIGURATION
CS
SCK
SDI
ISL23448
DCP1
WR
WR
SDO
16 CLKS
V
It is recommended to keep V
normal operation. In a case where turning V
necessary, it is recommended to ground the V
ISL23448. Grounding the V
not affect other devices on the same bus. It is good practice to put
a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to
the V
V
It is recommended to put a 1µF capacitor in parallel with 0.1µF
decoupling capacitor close to the V
D C P1
D C P2
N DCP IN A CHAIN
CC
LOGIC
LOGIC
Requirements and Placement
Requirements
pin.
CS
SCK
SDI
DCP2
SDO
WR
WR
WR
16 CLKS
D C P2
D C P1
D C P0
LOGIC
LOGIC
pin or both V
CC
powered all the time during
pin.
LOGIC
CS
SCK
SDI
LOGIC
DCP(N-1)
LOGIC
OFF is
and V
SDO
pin of the
August 19, 2011
CC
FN7905.0
does