LPC1787FBD208,551 NXP Semiconductors, LPC1787FBD208,551 Datasheet - Page 7
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
LPC1787FBD208,551
Manufacturer Part Number
LPC1787FBD208,551
Description
IC MCU 32BIT 512KB FLASH 208LQFP
Manufacturer
NXP Semiconductors
Series
LPC17xxr
Datasheet
1.LPC1774FBD208551.pdf
(117 pages)
Specifications of LPC1787FBD208,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
120MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
165
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Data Converters
A/D 8x12b, D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-7575
LPC1787FBD208,551
LPC1787FBD208,551
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1787FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
5. Block diagram
LPC178X_7X
Objective data sheet
Fig 1.
(1) Not available on all parts. See
Block diagram
LCD
EMC
(1)
slave
slave
debug
port
HIGH-SPEED
OSCILLATOR
GPIO INTERRUPT CONTROL
GPIO
RTC POWER DOMAIN
32 kHz
EVENT RECORDER
BACKUP REGISTERS
I-code
bus
WINDOWED WDT
APB slave group 0
slave
PIN CONNECT
CORTEX-M3
interface
12-bit ADC
TEST/DEBUG
TIMER 0/1
UART0/1
JTAG
INTERFACE
CAN 0/1
I
PWM0/1
SSP1
ARM
2
C0/1
Table
D-code
bus
All information provided in this document is subject to legal disclaimers.
2.
RTC
CRC
system
bus
MULTILAYER AHB MATRIX
slave
Rev. 2 — 27 May 2011
CONTROLLER
GPDMA
BRIDGE 0
AHB TO
LPC178x/7x
APB
master
slave
BRIDGE 1
ETHERNET
AHB TO
APB
slave
master
(1)
32-bit ARM Cortex-M3 microcontroller
512/256/128/64 kB
HOST
ACCELERATOR
QUADRATURE ENCODER
MOTOR CONTROL PWM
DEVICE/
FLASH
FLASH
SYSTEM CONTROL
APB slave group 1
USB
(1)
/OTG
master
USART4
SD/MMC
TIMER2/3
UART2/3
SSP0/2
slave
I
DAC
(1)
2
I
= connected to GPDMA
2
C2
S
LPC178x/7x
(1)
(1)
POWER CONTROL,
slave
slave
EEPROM
GENERATION,
4032 B/
FUNCTIONS
2016 B
SYSTEM
clocks and
CLOCK
controls
© NXP B.V. 2011. All rights reserved.
96/80/40 kB
(1)
SRAM
ROM
002aaf528
7 of 117
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