PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 200
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605F-page 198
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit =
REG
W
Carry bit =
REG
W
Q1
=
=
=
=
register ‘f’
ADD W and Carry bit to f
[ label ] ADDWFC
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(W) + (f) + (C) → dest
N, OV, C, DC, Z
Add W, the Carry flag and data
memory location ‘f’. If ‘d’ is ‘0’, the
result is placed in W. If ‘d’ is ‘1’, the
result is placed in data memory
location ‘f’. If ‘a’ is ‘0’, the Access
Bank will be selected. If ‘a’ is ‘1’, the
BSR will not be overridden.
1
1
ADDWFC
Read
Q2
0010
1
0x02
0x4D
0
0x02
0x50
00da
REG, W
Process
Data
Q3
ffff
f [,d [,a]]
destination
Write to
Q4
ffff
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
=
=
Read literal
AND literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
(W) .AND. k → W
N, Z
The contents of W are AND’ed with
the 8-bit literal ‘k’. The result is
placed in W.
1
1
ANDLW
0000
Q2
‘k’
0xA3
0x03
© 2007 Microchip Technology Inc.
1011
0x5F
Process
Data
Q3
k
kkkk
Write to W
Q4
kkkk
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