PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 225
PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
PC =
Q1
No
TOS
operation
operation
Return from Subroutine
[ label ]
s ∈ [0,1]
(TOS) → PC,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
is loaded into the program counter.
If ‘s’= 1, the contents of the shadow
registers, WS, STATUSS and
BSRS, are loaded into their corre-
sponding registers, W, Status and
BSR. If ‘s’ = 0, no update of these
registers occurs (default).
1
2
RETURN
0000
Q2
No
No
RETURN [s]
0000
operation
Process
Data
Q3
No
0001
from stack
operation
Pop PC
Q4
No
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
PIC18F1220/1320
Q1
=
=
=
=
=
register ‘f’
Rotate Left f through Carry
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n + 1>,
(f<7>) → C,
(C) → dest<0>
C, N, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
C
RLCF
01da
Process
Data
Q3
REG, W
register f
DS39605F-page 223
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
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