PIC18F4585-H/PT Microchip Technology, PIC18F4585-H/PT Datasheet - Page 151

• Manufacturer Part Number: PIC18F4585-H/PT
• Description: IC MCU 8BIT 48KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS2:T0PS0 bits
(T0CON<3:0>)
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When it is assigned, prescale values
from 1:2 through 1:256 in power-of-2 increments are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 11-1:
© 2007 Microchip Technology Inc.
TMR0L
TMR0H
INTCON
T0CON
TRISA
Legend: x = unknown, u = unchanged, — = unimplemented locations, read as ‘0’.
Note:
Name
Prescaler
Shaded cells are not used by Timer0.
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Module Low Byte Register
Timer0 Module High Byte Register
GIE/GIEH PEIE/GIEL TMR0IE
TMR0ON
Bit 7
which
REGISTERS ASSOCIATED WITH TIMER0
—
PORTA Data Direction Register
determine
T08BIT
Bit 6
the
T0CS
Bit 5
PIC18F2585/2680/4585/4680
prescaler
Preliminary
INT0IE
T0SE
Bit 4
11.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
11.4
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h in 8-bit mode, or
from FFFFh to 0000h in 16-bit mode. This overflow sets
the TMR0IF flag bit. The interrupt can be masked by
clearing the TMR0IE bit (INTCON<5>). Before re-
enabling the interrupt, the TMR0IF bit must be cleared
in software by the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
RBIE
Bit 3
PSA
Timer0 Interrupt
TMR0IF
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
INT0IF
T0PS1
Bit 1
T0PS0
RBIF
Bit 0
DS39625C-page 149
on page
Values
Reset
50
50
49
50
52