LPC1820FET100,551 NXP Semiconductors, LPC1820FET100,551 Datasheet - Page 10
LPC1820FET100,551
Manufacturer Part Number
LPC1820FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1820FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
168K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
P2_5
P2_6
P2_7
P2_8
P2_9
P2_10
P2_11
P2_12
P2_13
[3]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Pin description
K14
K16
H14
J16
H16
G16 I; PU
F16
E15
C16
…continued
Reset
state
[1]
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
I; PU
Type Description
-
I
I
I
-
I/O
I/O
O
I/O
O
I/O
I/O
-
O
I/O
I/O
I/O
O
I/O
I/O
I/O
O
O
I/O
I/O
O
I
I/O
I/O
O
-
I/O
I/O
I
-
I/O
All information provided in this document is subject to legal disclaimers.
n.c.
CTIN_2 — SCT input 2. Capture input 2 of timer 0.
USB1_VBUS — Monitors the presence of USB1 bus power.
Note: This signal must be HIGH for USB reset to occur.
ADCTRIG1 — ADC trigger input 1.
n.c.
U0_DIR — RS-485/EIA-485 output enable/direction control for USART0.
EXTBUS_A10 — External memory address line 10.
USB0_IND0 — USB0 port indicator LED control output 0.
GPIO0[7] — General purpose digital input/output pin.
CTOUT_1 — SCT output 1. Match output 1 of timer 0.
U3_UCLK — Serial clock input/output for USART3 in synchronous mode.
EXTBUS_A9 — External memory address line 9. Boot control pin 3 (see
Table
n.c.
CTOUT_0 — SCT output 0. Match output 0 of timer 0.
U3_DIR — RS-485/EIA-485 output enable/direction control for USART3.
EXTBUS_A8 — External memory address line 8. Boot control pin 2 (see
Table
GPIO1[10] — General purpose digital input/output pin.
CTOUT_3 — SCT output 3. Match output 3 of timer 0.
U3_BAUD3 — <tbd>for USART3.
EXTBUS_A0 — External memory address line 0.
GPIO0[14] — General purpose digital input/output pin.
CTOUT_2 — SCT output 2. Match output 2 of timer 0.
U2_TXD — Transmitter output for USART2.
EXTBUS_A1 — External memory address line 1.
GPIO1[11] — General purpose digital input/output pin.
CTOUT_5 — SCT output 5. Match output 1 of timer 1.
U2_RXD — Receiver input for USART2.
EXTBUS_A2 — External memory address line 2.
GPIO1[12] — General purpose digital input/output pin.
CTOUT_4 — SCT output 4. Match output 0 of timer 1.
n.c.
EXTBUS_A3 — External memory address line 3.
GPIO1[13] — General purpose digital input/output pin.
CTIN_4 — SCT input 4. Capture input 2 of timer 1.
n.c.
EXTBUS_A4 — External memory address line 4.
Rev. 1.2 — 17 February 2011
5). This pin must be HIGH on reset.
5).
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
© NXP B.V. 2011. All rights reserved.
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