LPC1820FET100,551 NXP Semiconductors, LPC1820FET100,551 Datasheet - Page 27
LPC1820FET100,551
Manufacturer Part Number
LPC1820FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1820FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
168K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
NXP Semiconductors
Table 3.
LPC1850_30_20_10
Objective data sheet
Symbol
TDI
I
I2C0_SCL
I2C0_SDA
USB0 pins
USB0_DP
USB0_DM
USB0_VBUS
USB0_ID
USB0_RREF
USB1 pins
USB1_DP
USB1_DM
Reset and wake-up pins
RESET
WAKEUP0
WAKEUP1
WAKEUP2
WAKEUP3
ADC pins
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
RTC
RTC_ALARM
RTCX1
RTCX2
2
C-bus pins
[2]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
[9]
[6]
[5]
[7]
[8]
[8]
[5]
[7]
Pin description
[5]
[6]
J4
L15
L16
F2
G2
F1
H2
H1
F12
G12 -
D9
A9
A10
C9
D8
E3
C3
A4
B5
C6
B3
A5
C5
A11
A8
B8
…continued
Reset
state
[1]
I; PU
I; F
I; F
-
-
-
-
-
-
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
I; IA
-
-
-
Type Description
I
I/O
I/O
I/O
I/O
I/O
I
-
I/O
I/O
I
I
I
I
I
-
-
-
-
-
-
-
-
-
-
-
All information provided in this document is subject to legal disclaimers.
Test Data In for JTAG interface.
I
I
USB0 bidirectional D+ line.
USB0 bidirectional D line.
VBUS pin (power on USB cable).
Indicates to the transceiver whether connected a A-device (ID LOW) or
B-device (ID HIGH).
USB connection for external reference resistor (12.0 k 1 %) to analog
ground supply.
USB1 bidirectional D+ line.
USB1 bidirectional D line.
External reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0.
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
ADC0/1 input channel 0. Shared between ADC0, ADC1, and DAC.
ADC0/1 input channel 1.
ADC0/1 input channel 2.
ADC0/1 input channel 3.
ADC0/1 input channel 4.
ADC0/1 input channel 5.
ADC0/1 input channel 6.
ADC0/1 input channel 7.
RTC controlled output.
Input to the RTC 32 kHz ultra-low power oscillator circuit.
Output from the RTC 32 kHz ultra-low power oscillator circuit.
2
2
C clock input/output. Open-drain output (for I
C data input/output. Open-drain output (for I
Rev. 1.2 — 17 February 2011
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2
2
C-bus compliance).
C-bus compliance).
© NXP B.V. 2011. All rights reserved.
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