ISL85033-12VEVAL3Z Intersil, ISL85033-12VEVAL3Z Datasheet - Page 16

• Manufacturer Part Number: ISL85033-12VEVAL3Z
• Description: EVAL BAORD FOR ISL85033
• Manufacturer: Intersil
• Series: -r

Specifications of ISL85033-12VEVAL3Z

• Main Purpose: DC/DC, Negative Inverter
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: -3.3 ~ -15 V
• Current - Output: 5A
• Voltage - Input: 4.5 ~ 28 V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz ~ 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL85033
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Detailed Description
The ISL85033 combines a standard buck PWM controller
with an integrated switching MOSFET. The buck controller
drives an internal N-Channel MOSFET and requires an
external diode to deliver load current up to 3A. A
Schottky diode is recommended for improved efficiency
and performance over a standard diode. The standard
buck regulator can operate from an unregulated DC
source, such as a battery, with a voltage ranging from
+4.5V to +28V. The converter output can be regulated to
as low as 0.8V. These features make the ISL85033
ideally suited for FPGA, set-top boxes, LCD panels, DVD
drives, and wireless chipset power applications.
The ISL85033 employs a peak current mode control loop
which simplifies feedback loop compensation and rejects
input voltage variation. External feedback loop
compensation allows flexibility in output filter component
selection. The regulator switches at a default 500kHz and
it can be adjusted from 300kHz to 2MHz with a resistor
from FS to GND. The ISL85033 is also synchronizable
from 300kHz to 2MHz.
Operation Initialization
The power-ON reset circuitry and enable inputs prevent
false start-up of the PWM regulator output. Once all
input criteria are met, the controller soft-starts the
output voltage to the programmed level.
Power-On Reset and Undervoltage Lockout
The ISL85033 automatically initializes upon receipt of
input power supply. The power-on reset (POR) function
continually monitors VIN1 voltage. While below the POR
threshold, the controller inhibits switching of the internal
power MOSFET. Once exceeded, the controller initializes
the internal soft-start circuitry. If VIN1 supply drops
below their falling POR threshold during soft-start or
operation, the buck regulator is disabled until the input
voltage returns.
Enable and Disable
When EN1 and EN2 are pulled low, the device enters
shutdown mode and the supply current drops to a
typical value of 20µA. All internal power devices are held
in a high-impedance state while in shutdown mode.
The EN pin enables the controller of the ISL85033. When
the voltage on the EN pin exceeds its logic rising
threshold, the controller initiates the 2ms soft-start
function for the PWM regulator. If the voltage on the EN
pin drops below the falling threshold, the buck regulator
shuts down.
Power Good
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage
via the FB pin. PG is actively held low when EN is low
and during the buck regulator soft-start period. After the
soft-start period terminates, PG becomes high
impedance as long as the output voltage (monitored on
the FB pin) is above 90% of the nominal regulation
16
ISL85033
ISL85033
voltage set by FB. When V
nominal regulation voltage, the ISL85033 pulls PG low.
Any fault condition forces PG low until the fault condition
is cleared by attempts to soft-start. There is an internal
5MΩ internal pull-up resistor.
Output Voltage Selection
The regulator output voltages is easily programmed
using an external resistor divider to scale V
to the internal reference voltage. The scaled voltage is
applied to the inverting input of the error amplifier; refer
to Figure 38.
The output voltage programming resistor, R
on the value chosen for the feedback resistor, R
the desired output voltage, V
Equation 1 describes the relationship between V
resistor values. R
10kΩ range.
If the desired output voltage is 0.8V, then R
unpopulated and R
Output Tracking and
Sequencing
Output tracking and sequencing between channels can
be implemented by using the SS1 and SS2 pins.
Figures 39, 40 and 41 show several configurations for
output tracking/sequencing for a 2.5V and 1.8V
application. Independent soft-start for each channel is
shown in Figure 39 and measured in Figure 29. The
output ramp-time for each channel (t
soft-start capacitor (C
Ratiometric tracking is achieved in Figure 40 by using
the same value for the soft-start capacitor on each
channel; it is measured in Figure 30.
By connecting a feedback network from V
SS2 pin with the same ratio that sets V
absolute tracking shown in Figure 41 is implemented.
The measurement is shown in Figure 31. If the output
of Channel 1 is shorted to GND, it will enter
overcurrent hiccup mode, SS2 will be pulled low
through the added resistor between VOUT1 and SS2
and this will force Channel 2 into hiccup as well. If the
output of Channel 2 is shorted to GND with VOUT1 in
C
R
SS
2
=
[
μF
(
FIGURE 38. EXTERNAL RESISTOR DIVIDER
V
]
OUT
=
2.5*t
–
0.8 ) R
SS
3
•
s ( )
EA
2
is often chosen to be in the 1kΩ to
REFERENCE
3
is zero ohm.
⁄
-
+
0.8
SS
0.8V
).
OUT
OUT
drops 10% below the
, of the regulator.
FB
R
R
SS
2
3
OUT2
) is set by the
OUT1
OUT
2
3
December 8, 2010
, depends
is left
voltage,
V
3
OUT
relative
OUT
, and
to the
(EQ. 1)
(EQ. 2)
FN6676.2
and