ISL85033-12VEVAL3Z Intersil, ISL85033-12VEVAL3Z Datasheet - Page 21

• Manufacturer Part Number: ISL85033-12VEVAL3Z
• Description: EVAL BAORD FOR ISL85033
• Manufacturer: Intersil
• Series: -r

Specifications of ISL85033-12VEVAL3Z

• Main Purpose: DC/DC, Negative Inverter
• Outputs And Type: 1, Non-Isolated
• Power - Output: -
• Voltage - Output: -3.3 ~ -15 V
• Current - Output: 5A
• Voltage - Input: 4.5 ~ 28 V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz ~ 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL85033
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 47 shows the type II compensator and its transfer
function is expressed as Equation 22:
Where:
the compensator design goal is:
High DC gain
Loop bandwidth f
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is shown in
Equation 24:
Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at
either ESR zero frequency or half switching frequency,
whichever is lower.
The loop gain T
gain. Therefore, the compensator resistance R
determined by Equation 25:
where g
amplifier, typically 200uA/V. Compensator capacitor C
then given by Equation 26:
Example: V
C
R
C
A
ω
Put compensator zero ω
o
1
v
1
cz1
( )
=
= 220µF/5mΩ, L = 5.6µH, g
S
=
2πf
-----------------------------------
=
=
----------------- C
R
R
R
1
-------------- -
R
2
3
v ˆ
---------------- -
g
1
ω
m
c
comp
v ˆ
1
m
V
cz
1
FB
C
FIGURE 47. TYPE II COMPENSATOR
o
V
is the trans-conductance of the voltage error
,
1
C
FB
IN
Vo
Vo
,
o
=
2
R
=
ω
= 12V, V
v
-------------------- -
C
T
cz2
(S) at crossover frequency of f
------------------------ -
2πR
1
C
g
c
+
:
3
m
V REF
V REF
V FB
V FB
=
C
1
1
cz1
2
-------------- -
R
⎛
⎝
f
esr
1
-- - to
4
2
1
⎛
⎝
---------------------------------------------------------
C
1
o
=
-
-
+
+
3
----- -
10
+
1
,
= 5V, I
21
GM
(
ω
------------ -
ω
⎞ f
⎠
1to3
S 1
cp
cz1
S
s
⎛
⎝
=
⎞ 1
⎠
+
)
⎛
⎝
---------------------- -
R
---------------- -
R
C
--------- -
ω
m
o
1
O
S
1
cp
R
1
C
+
C
C
= 3A, f
+
= 200µs, R
V COMP
V COMP
1
1
⎞
⎠
------------ -
ω
1
O
C
C
S
cz2
2
2
⎞
⎠
s
C
= 500kHz,
2
c
1
T
has unity
is
= 0.21,
(EQ. 24)
(EQ. 26)
(EQ. 25)
(EQ. 22)
(EQ. 23)
ISL85033
ISL85033
1
is
V
f
Put the compensator zero at 6.6kHz (~1.5x C
put the compensator pole at ESR zero, which is
1.45MHz. The compensator capacitors are:
C
parasitic capacitance from V
C
Figure 48A shows the simulated voltage loop gain. It is
shown that it has 80kHz loop bandwidth with 69° phase
margin and 15dB gain margin. Optional addition phase
boost can be added to the overall loop response by
using C
Rectifier Selection
Current circulates from ground to the junction of the
external Schottky diode and the inductor when the high-
side switch is off. As a consequence, the polarity of the
switching node is negative with respect to ground. This
voltage is approximately -0.5V (a Schottky diode drop)
during the off-time. The rectifier's rated reverse
breakdown voltage must be at least equal to the
maximum input voltage, preferably with a 20% derating
factor. The power dissipation when the Schottky diode
conducts is expressed in Equation 27:
P
c
FB
1
2
D
= 80kHz, then compensator resistance R
[
100
= 470pF, C
is optional).
-15
-30
-20
W
60
45
30
15
80
60
40
20
= 0.8V, S
0
0
]
100
100
=
3
.
I
OUT
⋅
e
V
2
1•10
1•10
= 1.1×10
D
= 3pF (There is approximately 3pF
⋅
⎛
⎜
⎝
3
3
1
–
FIGURE 48B.
FIGURE 48A.
V
--------------- -
V
OUT
PHASE (°)
IN
5
1•10
1•10
V/s, S
⎞
⎟
⎠
COMP
GAIN (dB)
4
4
n
= 3.4×10
to GND; therefore,
1•10
1•10
5
5
December 8, 2010
5
1
V/s,
o
= 72kΩ.
1•10
1•10
R
(EQ. 27)
o)
FN6676.2
, and
6
6