AD8150AST Analog Devices Inc, AD8150AST Datasheet

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AD8150AST

Manufacturer Part Number
AD8150AST
Description
IC CROSSPOINT SWIT 33X17 184LQFP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD8150AST

Rohs Status
RoHS non-compliant
Function
Crosspoint Switch
Circuit
1 x 33:17
Voltage Supply Source
Dual Supply
Voltage - Supply, Single/dual (±)
±3 V ~ 5.5 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
184-LQFP
Number Of Arrays
1
Differential Data Transmission
Yes
Operating Supply Voltage (typ)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
85C
Cascading Capability
No
Line Code
NRZ
On-chip Buffers
Yes
On-chip Mux/demux
No
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (typ)
3.3V
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD8150AST
Manufacturer:
AD
Quantity:
10
Part Number:
AD8150AST
Manufacturer:
ADI
Quantity:
210
Part Number:
AD8150ASTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
FEATURES
Low cost
33 × 17, fully differential, nonblocking array
>1.5 Gbps per port NRZ data rate
Wide power supply range: +5 V, +3.3 V, −3.3 V, −5 V
Low power
PECL and ECL compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter: <50 ps p-p
No heat sinks required
Drives a backplane directly
Programmable output current
Individual output disable for busing and building
Larger arrays
Double row latch
Buffered inputs
Available in 184-lead LQFP
APPLICATIONS
HD and SD digital video
Fiber optic network switching
GENERAL DESCRIPTION
AD8150 is a member of the Xstream line of products and is a
breakthrough in digital switching, offering a large switch array
(33 × 17) on very little power, typically less than 1.5 W.
Additionally, it operates at data rates in excess of 1.5 Gbps per
port, making it suitable for HDTV applications. Further, the
pricing of the AD8150 makes it affordable enough to be used
for SD applications. The AD8150 is also useful for OC-24
optical network switching.
The AD8150’s flexible supply voltages allow the user to operate
with either PECL or ECL data levels and will operate down to
3.3 V for further power reduction. The control interface is
CMOS/TTL compatible (3 V to 5 V).
Its fully differential signal path reduces jitter and crosstalk while
allowing the use of smaller single-ended voltage swings. The
AD8150 is offered in a 184-lead LQFP package that operates
over the industrial temperature range of 0°C to 85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
400 mA (outputs enabled)
30 mA (outputs disabled)
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
UPDATE
RESET
WE
–500mV
CS
RE
100mV/
D
A
500mV
DIV
7
5
FUNCTIONAL BLOCK DIAGRAM
33 × 17, 1.5 Gbps Digital
Figure 2. Output Eye Pattern, 1.5 Gbps
Figure 1. Functional Block Diagram
© 2005 Analog Devices, Inc. All rights reserved.
LATCH
FIRST
RANK
7-BIT
17
Crosspoint Switch
SECOND
100ps/DIV
LATCH
RANK
7-BIT
17
33
AD8150
DIFFERENTIAL
INP
www.analog.com
SWITCH
MATRIX
33
AD8150
17
33
INN
17
17
OUTP
OUTN

Related parts for AD8150AST

AD8150AST Summary of contents

Page 1

FEATURES Low cost 33 × 17, fully differential, nonblocking array >1.5 Gbps per port NRZ data rate Wide power supply range +3.3 V, −3.3 V, −5 V Low power 400 mA (outputs enabled (outputs disabled) PECL ...

Page 2

AD8150 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Maximum Power Dissipiation .................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 9 Test Circuit ...................................................................................... 13 Control Interface............................................................................. 14 Control Interface Truth Tables ...

Page 3

SPECIFICATIONS At 25° 3 Table 1 Parameter DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) Channel Jitter RMS Channel Jitter Propagation Delay Propagation Delay Match Output Rise/Fall Time INPUT ...

Page 4

AD8150 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage V − Internal Power Dissipation AD8150 184-Lead Plastic LQFP (ST) Differential Input Voltage Output Short-Circuit Duration 2 Storage Temperature Range 1 Specification is for device in free ...

Page 5

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IN20P 2 INDICATOR IN20N IN21P 5 IN21N IN22P 8 IN22N IN23P 11 IN23N IN24P ...

Page 6

AD8150 Table 3. Pin Function Descriptions Pin No. Mnemonic 10, 13, 16, 19, 22, 25, 28, 31, V 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, 129, ...

Page 7

Pin No. Mnemonic OUT09N 67 OUT09P OUT08N 70 OUT08P OUT07N 73 OUT07P OUT06N 76 OUT06P OUT05N 79 OUT05P OUT04N 82 OUT04P 83 ...

Page 8

AD8150 Pin No. Mnemonic 131 IN10N 133 IN11P 134 IN11N 136 IN12P 137 IN12N 140 IN13P 141 IN13N 143 IN14P 144 IN14N 146 IN15P 147 IN15N 150 V 151 REF 152 V 153 D6 154 D5 155 D4 156 D3 ...

Page 9

TYPICAL PERFORMANCE CHARACTERISTICS 100 V = –3.3V (V – 800mV PK- RMS 0 0 –0.2 –0.4 –0.6 –0.8 V (V) OH Figure 5. Jitter vs. V 1.5 Gbps, PRBS 23 OH ...

Page 10

AD8150 100 V = –3. PK- RMS (mA) OUT Figure 11. Jitter vs. I 1.5 Gbps, PRBS 23 OUT 100 V = –3. PK- ...

Page 11

DELAY (ps) Figure 17. Variation in Channel-to-Channel Delay, All 561 Points 17.0 16.5 16.0 15.5 15.0 14.5 –3.3 –3.6 –3.9 –4.2 V (V) EE Figure 18. I ...

Page 12

AD8150 500mV –500mV 200ps/DIV Figure 23. Eye Pattern −3.3 V, 1.5 Gbps PRBS 23 EE 500mV –500mV Figure 24. Eye Pattern, V Rev Page 100ps/DIV = −5 V, 1.5 Gbps PRBS 23 EE ...

Page 13

TEST CIRCUIT GENERATOR INTRINSIC JITTER OF HP8133A AND TEKTRONIX 11801B = 3ps RMS, 17ps PK- 50Ω L 1.65kΩ AD8150 P P HP8133A PRBS IN OUT 105Ω ...

Page 14

AD8150 CONTROL INTERFACE CONTROL INTERFACE TRUTH TABLES The following are truth tables for the control interface. Table 4. Basic Control Functions Control Pins RESET UPDATE Function Global Reset. Reset all second-rank enable ...

Page 15

CONTROL INTERFACE TIMING DIAGRAMS CS INPUT WE INPUT A[4:0] INPUTS D[6:0] INPUTS Table 6. First-Rank Write Cycle Symbol t Setup Time CSW t ASW t DSW t Hold Time CHW t AHW t DHW t Width of Write Enable Pulse ...

Page 16

AD8150 CS INPUT UPDATE INPUT ENABLING OUT[0:16][N:P] OUTPUTS TOGGLE OUT[0:16][N:P] OUTPUTS DISABLING OUT[0:16][N:P] OUTPUTS Table 7. Second-Rank Update Cycle Symbol t Setup Time CSU t Hold Time CHU t Output Enable Times UOE t Output Toggle Times UOT t Output ...

Page 17

CS INPUT UPDATE INPUT WE INPUT ENABLING OUT[0:16][N:P] OUTPUTS DISABLING OUT[0:16][N:P] OUTPUTS Table 8. First-Rank Write Cycle and Second-Rank Update Cycle Symbol t Setup Time CSU t Hold Time CHU t Output Enable Times UOE 1 t WOE t Output ...

Page 18

AD8150 CS INPUT RE INPUT A[4:0] INPUTS D[6:0] OUTPUTS Table 9. Second-Rank Readback Cycle Symbol t Setup Time CSR t Hold Time CHR t RHA t Enable Time RDE t Access Time AA t Release Time RDD ADDR 1 ADDR ...

Page 19

RESET INPUT DISABLING OUT[0:16][N:P] OUTPUTS Table 10. Asynchronous Reset Symbol t Disable Time TOD t Width of Reset Pulse TW t TOD t TW Figure 30, Asynchronous Reset Parameter Output disable from reset Rev Page ...

Page 20

AD8150 CONTROL INTERFACE PROGRAMMING EXAMPLE The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock period ns possible to accelerate the execution ...

Page 21

CONTROL INTERFACE DESCRIPTION The AD8150 control interface receives and stores the desired connection matrix for the 33 input and 17 output signal pairs. The interface consists of 17 rows of double-rank 7-bit latches, one row for each output. The 7-bit ...

Page 22

AD8150 RE Input Second-rank read enable. Forcing this pin to logic low enables the output drivers on the bidirectional D[6:0] pins, entering the readback mode of operation. By selecting an output address with the A[4:0] pins and forcing RE to ...

Page 23

CIRCUIT DESCRIPTION The AD8150 is a high speed 33 × 17 differential crosspoint switch designed for data rates up to 1.5 Gbps per channel. The AD8150 supports PECL-compatible input and output levels when operated from supply (V ...

Page 24

AD8150 V CC OUTyyP V – DISABLE Figure 34. Simplified Output Circuit To ensure proper operation, all outputs (including unused output) must be pulled high, using external pull-up networks level within the ...

Page 25

The resistor value current is given by the following expression SET I OUT Example kΩ for SET OUT The minimum set resistor ...

Page 26

AD8150 0.01μ 0.01μ C29 0.01μF C31 0.01μF PIN 1 IN20P 2 INDICATOR V CC IN20N IN21P 5 IN21N IN22P 8 V ...

Page 27

POWER DISSIPATION For analysis, the power dissipation of the AD8150 can be divided into three separate parts. These are the control logic, the data path circuits, and the (ECL or PECL) outputs, which are part of the data path circuits, ...

Page 28

AD8150 HEAT SINKING Depending on several factors in its operation, the AD8150 can dissipate more. The part is designed to operate without the need for an explicit external heat sink. However, the package design offers enhanced heat ...

Page 29

APPLICATIONS AD8150 INPUT AND OUTPUT BUSING Although the AD8150 is a digital part, in any application that runs at high speed, analog design details will have to be given very careful consideration. At high data rates, the design of the ...

Page 30

AD8150 EVALUATION BOARD An evaluation board has been designed and is available to rapidly test the main features of the AD8150. This board lets the user analyze the analog performance of the AD8150 channels and easily control the configuration of ...

Page 31

After this, the PC keyboard’s left or right arrow key can be held down to generate a steady stream of programming signals out of the parallel port. The CLOCK test point on the AD8150 evaluation board can be monitored with ...

Page 32

AD8150 PCB LAYOUT Figure 43. Component Side Rev Page ...

Page 33

Figure 44. Circuit Side Rev Page AD8150 ...

Page 34

AD8150 Figure 45. Silkscreen Top Rev Page ...

Page 35

Figure 46. Solder Mask Top Rev Page AD8150 ...

Page 36

AD8150 Figure 47. Silkscreen Bottom Rev Page ...

Page 37

Figure 48. Solder Mask Bottom Rev Page AD8150 ...

Page 38

AD8150 Figure 49. INT1 ( Rev Page ...

Page 39

Figure 50. INT2 ( Rev Page AD8150 ...

Page 40

AD8150 R19 R40 R58 1.65kΩ 1.65kΩ 1.65kΩ IN00P IN06P IN12P P4 P16 P28 R20 R57 R39 105Ω 105Ω 105Ω P5 P17 P29 IN00N IN06N R38 R56 IN12N R21 1.65kΩ 1.65kΩ 1.65kΩ ...

Page 41

CLK CLK P2 6 74HC14 DATA 1 OUT_EN DATA 74HC14 74HC14 ...

Page 42

... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW 1 ORDERING GUIDE Model Temperature Range AD8150AST 0°C to 85°C 2 AD8150ASTZ 0°C to 85°C AD8150-EVAL 1 Details of lead finish composition can be found on the ADI website Pb-free part. 22.20 0.75 22.00 SQ 1.60 0.60 21.80 MAX ...

Page 43

NOTES Rev Page AD8150 ...

Page 44

AD8150 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01074–0–9/05(A) Rev Page ...

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