AD8150AST Analog Devices Inc, AD8150AST Datasheet - Page 22

• Manufacturer Part Number: AD8150AST
• Description: IC CROSSPOINT SWIT 33X17 184LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD8150AST

• Rohs Status: RoHS non-compliant
• Function: Crosspoint Switch
• Circuit: 1 x 33:17
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 184-LQFP
• Number Of Arrays: 1
• Differential Data Transmission: Yes
• Operating Supply Voltage (typ): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Cascading Capability: No
• Line Code: NRZ
• On-chip Buffers: Yes
• On-chip Mux/demux: No
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (typ): 3.3V
• Lead Free Status / RoHS Status: Not Compliant

AD8150
RE Input
Second-rank read enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D[6:0] pins, entering the
readback mode of operation. By selecting an output address
with the A[4:0] pins and forcing RE to logic low, the 7-bit data
stored in the second-rank latch for that output address will be
written to the D[6:0] pins. Data should not be written to the
D[6:0] pins externally while in readback mode. The RE and WE
pins are not exclusive and may be used at the same time, but
data should not be written to the D[6:0] pins from external
sources while in readback mode.
CS Input
Chip select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described below. This pin has no effect on the
signal pairs and does not alter any of the stored control data.
RESET Input
Global output disable pin. Forcing the RESET pin to logic low
will reset the enable bit, D6, in all 17 second-rank latches,
regardless of the state of any other pins. This has the effect of
immediately disabling the 17 output signal pairs in the matrix.
Rev. A | Page 22 of 44
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8150 in a system that has multiple output
signal pairs connected together. Failure to do this may result in
several signal outputs contending after power-up. The reset pin
is not gated by the state of the chip-select pin, CS . It should be
noted that the RESET pin does not program the first rank,
which will contain undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8150 control interface has two supply pins, V
The potential between the positive logic supply V
negative logic supply V
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above V
CMOS and TTL logic drivers.
The signal matrix supplies, V
of the voltage on V
V
control interface on 3 V or 5 V while the signal matrix is
operated on 3.3 V or 5 V PECL, or on −3.3 V or −5 V ECL.
EE
) ≤ 10 V. These constraints will allow operation of the
SS
, allowing the interface to be used with most
DD
and V
SS
must be at least 3 V and no more than
SS
CC
, with the constraints that (V
and V
EE
, can be set independent
DD
and the
DD
and V
DD
−
SS
.