AK4125VFP-E2 AKM Semiconductor Inc, AK4125VFP-E2 Datasheet - Page 19

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AK4125VFP-E2

Manufacturer Part Number
AK4125VFP-E2
Description
IC SAMPLE RATE CONVERTER 30VSOP
Manufacturer
AKM Semiconductor Inc
Series
-r
Type
Sample Rate Converterr
Datasheet

Specifications of AK4125VFP-E2

Applications
Automotive Systems, Home Theater, TV
Mounting Type
Surface Mount
Package / Case
30-LSSOP (0.220", 5.60mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
974-1042-2
The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2.
Table
dependent on the IBICK input frequency.
[Input PORT in slave mode]
1. When using ILRCK
2. When using IBICK
[Input PORT in master mode]
1. When IMCLK is 256fs, 384fs, 512fs or 768fs, any external parts shown in
2. When IMCLK is 128fs or 192fs, the external parts shown in
MS0379-E-05
PLL Loop Filter
- Note. Smaller value can be selected for the capacitors (C1, C2) in case of ILRCK range from 16kHz to 216kHz..
Note. The IBCIK must be continuous except when the clocks are changed.
Note. IBCIK = 32fsi is supported only 16bit LSB justified and I
6,
Table
PLL2
PLL2
H
L
L
L
7) Please be careful the noise onto the FILT pin. When using IBICK, the value of external element is not
PLL1
PLL1
H
L
L
*
Table 7. PLL Loop Filter (IBICK Mode, *: Don’t care)
PLL0
PLL0
H
L
L
*
Table 6. PLL Loop Filter (ILRCK Mode)
16k ∼ 216kHz
16k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
8k ∼ 216kHz
Figure 14. PLL Loop Filter
8k ∼ 96kHz
AK4125
ILRCK
ILRCK
FILT
- 19 -
C1
R
Table 7
AVSS
1.8k ± 5%
1.5k ± 5%
1.5k ± 5%
470 ± 5%
1k ± 5%
1k ± 5%
R [Ω]
R [Ω]
2
S Compatible.
are required.
C2
Figure 14
0.68 ± 30%
0.68 ± 30%
0.68 ± 30%
0.22 ± 30%
1.0 ± 30%
1.0 ± 30%
C1 [μF]
C1 [μF]
are not required.
0.68 ± 30%
0.68 ± 30%
0.68 ± 30%
2.2 ± 30%
2.2 ± 30%
1.0 ± 30%
C2 [nF]
C2 [nF]
(Figure
[AK4125]
2010/05
14,

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