SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet - Page 12
![](/photos/31/27/312732/16pin_soic_n_sml.jpg)
SI3018-F-GSR
Manufacturer Part Number
SI3018-F-GSR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3018-F-GSR.pdf
(111 pages)
Specifications of SI3018-F-GSR
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Si3050 + Si3018/19
Table 8. Switching Characteristics—PCM Highway Serial Interface
(V
12
Parameter
Cycle Time PCLK
Valid PCLK Inputs
FSYNC Period
PCLK Duty Cycle
PCLK Jitter-Tolerance
FSYNC Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX Transition
Delay Time, PCLK Rise to DTX Tri-State
Setup Time, FSYNC Rise to PCLK Fall
Hold Time, PCLK Fall to FSYNC Fall
Setup Time, DRX Transition to PCLK Fall
Hold Time, PCLK Falling to DRX Transition
Notes:
D
=
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
3.0 to 3.6 V, T
times are referenced to the 20% and 80% levels of the waveform.
1
2
FSYNC
PCLK
DRX
DTX
A
Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)
=
0 to 70 °C for K-Grade, C
t
su1
t
d1
3
t
h1
Symbol
L
=
t
t
t
t
t
jitter
jitter
t
t
t
t
t
t
su1
su2
dty
t
t
d1
d2
d3
h1
h2
fp
t
20 pF)
p
r
f
Rev. 1.31
t
su2
t
d2
Conditions
t
p
t
Test
h2
t
fp
Min
122
40
25
20
25
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IH
= V
O
– 0.4 V, V
1.024
1.536
2.048
4.096
8.192
Typ
256
512
768
125
50
—
—
—
—
—
—
—
—
—
—
—
—
t
d3
IL
=
0.4 V, rise and fall
3906
±120
Max
60
25
25
20
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
2
Units
MHz
MHz
MHz
MHz
MHz
kHz
kHz
kHz
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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