SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet - Page 90
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SI3018-F-GSR
Manufacturer Part Number
SI3018-F-GSR
Description
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3018-F-GSR.pdf
(111 pages)
Specifications of SI3018-F-GSR
Lead Free Status / Rohs Status
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Register 43. Line Current/Voltage Threshold Interrupt (Si3019 line-side only)
Reset settings = 0000_0000
Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 line-side only)
Reset settings = 0000_0000
Bit
7:0
Bit
7:4
3
2
1
0
Name
Name
Type
Type
Bit
Bit
Reserved Read returns zero.
CVT[7:0]
Name
Name
CVM
CVS
CVP
CVI
D7
D7
Current/Voltage Threshold.
These bits determine the threshold at which an interrupt is generated from either the LCS or
LVS register. This interrupt can be generated to occur when the line current or line voltage
rises above or drops below the value in the CVT[7:0] register.
Current/Voltage Interrupt.
0 = The current/voltage threshold has not been crossed.
1 = The current/voltage threshold is crossed. If the CVM and INTE bits are set, a hardware
interrupt occurs on the AOUT/INT pin. Once set, this bit must be written to 0 to be cleared.
Current/Voltage Select.
0 = The line current shown in the LCS2 register is used to generate an interrupt.
1 = The line voltage shown in the LVS register is used to generate an interrupt.
Current/Voltage Interrupt Mask.
0 = The current/voltage threshold being triggered does not cause a hardware interrupt on the
AOUT/INT pin.
1 = The current/voltage threshold being triggered causes a hardware interrupt on the
AOUT/INT pin.
Current/Voltage Interrupt Polarity.
0 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register falling below the value in the CVT[7:0] register.
1 = The current/voltage threshold is triggered by the absolute value of the number in either
the LCS2 or LVS register rising above the value in the CVT[7:0] register.
D6
D6
D5
D5
Rev. 1.31
D4
D4
CVT[7:0]
R/W
Function
Function
R/W
CVI
D3
D3
Si3050 + Si3018/19
CVS
R/W
D2
D2
CVM
R/W
D1
D1
CVP
R/W
D0
D0
91
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