NAND512R3A2SZA6E Micron Technology Inc, NAND512R3A2SZA6E Datasheet - Page 11

• Manufacturer Part Number: NAND512R3A2SZA6E
• Manufacturer: Micron Technology Inc

Specifications of NAND512R3A2SZA6E

• Cell Type: NAND
• Density: 512Mb
• Access Time (max): 15us
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 26b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: VFBGA
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.95V
• Word Size: 8b
• Number Of Words: 64M
• Supply Current: 15mA
• Mounting: Surface Mount
• Pin Count: 63
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Numonyx SLC SP 70 nm
2
Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory array is organized in blocks where each block contains 32 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store error correction codes, software
flags or bad block identification.
In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and
a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area
and an 8 Word spare area. Refer to
Bad blocks
The NAND Flash 528 Byte/264 Word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to
management
Table 4
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to
Table 4.
shows the minimum number of valid blocks in each device. The values shown
Density of device
Valid blocks
for more details).
512 Mbit
Section 7: Software
210403 - Rev 3
Figure 5: Memory array
4016
Min
algorithms).
organization.
Section 7.1: Bad block
Memory array organization
4096
Max
11/51