NAND512R3A2SZA6E Micron Technology Inc, NAND512R3A2SZA6E Datasheet - Page 18

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NAND512R3A2SZA6E

Manufacturer Part Number
NAND512R3A2SZA6E
Description
Manufacturer
Micron Technology Inc
Datasheet

Specifications of NAND512R3A2SZA6E

Cell Type
NAND
Density
512Mb
Access Time (max)
15us
Interface Type
Parallel
Boot Type
Not Required
Address Bus
26b
Operating Supply Voltage (typ)
1.8V
Operating Temp Range
-40C to 85C
Package Type
VFBGA
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
1.7V
Operating Supply Voltage (max)
1.95V
Word Size
8b
Number Of Words
64M
Supply Current
15mA
Mounting
Surface Mount
Pin Count
63
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Command set
5
18/51
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in
Table 10.
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
2. Any undefined command sequence is ignored by the device.
3. The Read B command (code 01h) is not used in x16 devices.
4. The Program Confirm command (code 10h) is no more necessary for 512 Mbit, 70 nm devices. It is
Read A
Read B
Read C
Read Electronic Signature
Read Status Register
Page Program
Copy Back Program
Block Erase
Reset
input/output data are not shown.
optional and has been maintained for backward compatibility.
(3)
Command
Commands
210403 - Rev 3
1
Table
st
FFh
00h
01h
50h
90h
70h
80h
00h
60h
cycle
Bus write operations
10.
2
nd
D0h
8Ah
10h
cycle
(1)(2)
3
(10h)
rd
cycle
Numonyx SLC SP 70 nm
(4)
accepted during
Command
busy
Yes
Yes

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