STEVAL-ISV005V1 STMicroelectronics, STEVAL-ISV005V1 Datasheet - Page 11

• Manufacturer Part Number: STEVAL-ISV005V1
• Description: BOARD DEMONSTRATION FOR SPV1020
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STEVAL-ISV005V1

• Main Purpose: Power Management, Battery Charger Solar Powered
• Embedded: No
• Utilized Ic / Part: SPV1020, SEA05
• Primary Attributes: Built in MPPT (Max Power Point Tracking) and Soft Start
• Secondary Attributes: I/O Overcurrent Control, Output Overvoltage Control
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 497-11764

SPV1020
5.6
5.7
5.8
5.9
5.10
Over temperature protection OTP
When the temperature sensed at silicon level reaches 150 °C all low side power switches
are immediately turned OFF. The device becomes operative again as soon as the silicon
temperature falls down to 130 °C.
Shut-down
In shutdown mode (SHUT pin high) the converter is switched off to minimize the power
consumption. The synchronous rectifier intrinsic body diode causes a parasitic path
between input power supply and output, that cannot be avoided also in shutdown.
Under voltage lock-out (UVLO)
When solar radiation is too low or the PV cells are shaded, the energy generated could be
not enough to trigger the converter. In this case, until the input voltage remains lower than
the UVLO threshold, all the circuitry is in OFF state, avoiding undesired power consumption.
A hysteresis has been implemented in order to limit undesired switching of the internal
reset.
MPPT
In order to maximize the energy transferred from the PV cell string to the DC bus (connected
to the output of the converter) the converter embeds a logic running a Perturb&Observe
MPPT algorithm based on the monitoring of the voltage and current supplied by the PV
cells: if the operating voltage of the PV array is perturbed in a given direction and if the
power drawn from the PV array increases, this means that the operating point has moved
towards the MPP and, therefore, the operating voltage must be further perturbed in the
same direction. Otherwise, if the power drawn from the PV array decreases, the operating
point has moved away from the MPP and, therefore, the direction of the operating voltage
perturbation must be reversed
SPI
The SPV1020 embeds a 4-pin compatible SPI interface. The SPI allows full duplex,
synchronous, serial communication between a host controller (the master) and the
SPV1020 peripheral device (the slave). The SPI master provides the synchronizing clock
and starts all the communications. The idle state of the serial clock for the SPV1021 is high,
while data pins are driven on the falling edges of the serial clock and they are sampled on its
rising edges. These features correspond to a clock polarity set to 1 (typical host SPI control
bit CPOL=1) and to a clock phase set to 1 (typical host SPI control bit CPHA=1)
respectively. The bit order of each byte is MSB first.
When the master initiates a transmission, a data byte is shifted out through the MOSI pin to
the slave, while another data byte is shifted out through the MISO pin to the master; the
master controls the serial clock on the SCLK pin. The SS (active low) pin must be driven low
by the master during each transmission. The bit order of each byte is MSB first.
The SPV1020 register file is accessible by the host through the SPI bus. Thus, the host can
read some register of SPV1020 control parameters. Each data frame includes at least one
Doc ID 17588 Rev 2
Detailed description
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