MT48LC4M32B2TG-7 IT:GTR Micron Technology Inc, MT48LC4M32B2TG-7 IT:GTR Datasheet - Page 26
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MT48LC4M32B2TG-7 IT:GTR
Manufacturer Part Number
MT48LC4M32B2TG-7 IT:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M32B2TG-7_ITGTR.pdf
(67 pages)
Specifications of MT48LC4M32B2TG-7 IT:GTR
Organization
4Mx32
Density
128Mb
Address Bus
14b
Access Time (max)
17/8/5.5ns
Maximum Clock Rate
143MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
175mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Not Compliant
Figure 14:
PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
READ-to-PRECHARGE
Notes:
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL - 1. This is shown in Figure 14 for each
possible CL; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until
hidden during the access of the last data element(s).
COMMAND
COMMAND
1. DQM is LOW.
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
COMMAND
ADDRESS
ADDRESS
ADDRESS
CLK
CLK
CLK
DQ
DQ
DQ
BANK a,
BANK a,
BANK a,
COL n
COL n
COL n
T0
T0
T0
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
CL = 3
OUT
n
T2
T2
T2
NOP
NOP
NOP
D
n + 1
D
OUT
OUT
n
26
T3
T3
T3
NOP
NOP
NOP
D
n + 2
t
D
D
n + 1
RP is met. Note that part of the row precharge time is
OUT
OUT
OUT
n
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK
BANK
BANK
T4
T4
T4
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
D
n + 2
n + 3
OUT
OUT
t RP
t RP
t RP
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
ROW
ROW
ROW
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition