MT48LC4M32B2TG-7 IT:GTR Micron Technology Inc, MT48LC4M32B2TG-7 IT:GTR Datasheet - Page 41

• Manufacturer Part Number: MT48LC4M32B2TG-7 IT:GTR
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48LC4M32B2TG-7 IT:GTR

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 17/8/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 175mA
• Pin Count: 86
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Not Compliant

PDF: 09005aef80872800/Source: 09005aef80863355
128MbSDRAMx32_2.fm - Rev. L 1/09 EN
10. For a READ without auto precharge interrupted by a READ (with or without auto pre-
11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-
12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge),
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge),
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or
8. Concurrent auto precharge: Bank n will initiate the auto precharge command when its
9. Burst in bank n continues as initiated.
WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.
burst has been interrupted by bank m’s burst.
charge), the READ to bank m will interrupt the READ on bank n, CL later (see Figure 10 on
page 23).
charge), the WRITE to bank m will interrupt the READ on bank n when registered (see
Figures 12 and 13 on page 25). DQM should be used one clock prior to the WRITE command
to prevent bus contention.
charge), the READ to bank m will interrupt the WRITE on bank n when registered (see
Figure 20 on page 30), with the data-out appearing CL later. The last valid WRITE to bank n
will be data-in registered one clock prior to the READ to bank m.
charge), the WRITE to bank will interrupt the WRITE on bank n when registered (see
Figure 18 on page 29). The last valid WRITE to bank n will be data-in registered one clock
prior to the READ to bank m.
the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n
will begin when the READ to bank m is registered (see Figure 27 on page 35).
the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be
used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE
to bank n will begin when the WRITE to bank m is registered (see Figure 28 on page 35).
the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out
appearing CL later. The PRECHARGE to bank n will begin after
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in
registered one clock prior to the READ to bank m (see Figure 29 on page 36).
the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE
to bank n will begin after
istered. The last valid WRITE to bank n will be data registered one clock to the WRITE to
bank m (see Figure 30 on page 36).
t
WR is met, where
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR begins when the WRITE to bank m is reg-
t
WR is met, where
©2001 Micron Technology, Inc. All rights reserved.
128Mb: x32 SDRAM
Register Definition
t
WR