AM186CC-50KD\W C AMD (ADVANCED MICRO DEVICES), AM186CC-50KD\W C Datasheet - Page 93

• Manufacturer Part Number: AM186CC-50KD\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-50KD\W C

• Lead Free Status / Rohs Status: Compliant

Pin List Table Column Definitions
The following paragraphs describes the individual
columns of information in Table 35, “Pin List Summary,”
on page A-12. The pins are grouped alphabetically by
function.
Note: All maximum delay numbers should be in-
creased by 0.035 ns for every pF of load (up to a max-
imum of 150 pF) over the maximum load specified in
Table 35 on page A-12.
Column #1—Signal Name, [Alternate Function],
{Pinstrap}
This column denotes the primar y and alternate
functions of the pins. Most of the pins that have
alternate functions are configured for these functions
via firmware modifying values in the Peripheral Control
B l o c k .
Microcontrollers Register Set Manual , order #21916,
for full documentation of this process.
Brackets, [ ], are used to indicate the alternate,
multiplexed function of a pin (i.e., not power-on reset
default).
Braces, { }, are used to indicate the functionality of a pin
only during a processor reset. These signals are called
pinstraps. To select the desired configuration, the
pinstraps are terminated internally with pullup resistors
or externally with pulldown resistors. Their state is
sampled during a processor reset and latched on the
rising edge of reset. The signals must be held in the
desired state for 4.5 system clock cycles after the
deassertion of reset. Based on the pinstrap’s state at
the time they are latched, certain features of the
Am186CC controller are enabled or disabled. All
external termination should be implemented with 10-
kohm resistors on these signals.
T h e pi ns tr a p s a r e l i s t e d i n Ta bl e 3 1 , “ R e s e t
Configuration Pins (Pinstraps),” on page A-10.
Column #2—Pin No.
The pin number column identifies the pin number of the
individual I/O signal on the package.
Column #3—Type
Definitions of the abbreviations in the Type column are
shown in Table 34.
R e f e r
t o
t h e
Am186™CC Communications Controller Data Sheet
A m 1 8 6 ™ C C / C H / C U
Column #4—Max Load (pF)
The Max Load column designates the capacitive load
at which the I/O timing for that pin is guaranteed.
Column #5—POR Default Function
The POR Default Function column shows the status of
these pins after a power-on reset. In some cases the
pin is the function outlined in the “Signal Name” column
of the table. The signal name is listed in the POR
Default Function column if the signal is the default
function and not a PIO after a processor reset. In other
cases the pin is a PIO configured as an input.
Column #6—Reset State
The Reset State column indicates the termination
present on the signal at reset (pullup or pulldown) and
indicates whether the signal is a three-stated output or
a Sc hmitt tr igger input. Refer to Table 34 for
abbreviations used in this column.
Column #7—POR Default Operation
The POR Default Operation column describes the type
of input and/or output that is default pin operation.
Refer to Table 34 for abbreviations used in this column.
Column #8—Hold State
The Hold State column shows the state of the pin in
hold state. Refer to Table 34 for abbreviations used in
this column.
Column #9—5 V
A "5 V" in the 5-V column indicates 5-V tolerant inputs.
These inputs are not damaged and do not draw excess
power when driven with levels up to V
These pins only drive to V
STI-OD
OD-O
Type
STI
OD
PD
PU
TS
LS
{ }
[ ]
H
O
B
Table 34. Pin List Table Definitions
Definition
Pin alternate function
Pinstrap pin
Bidirectional
High
Programmable to hold last state of pin
Totem pole output
Open drain output
Open drain output or totem pole output
Internal pulldown resistor
Internal pullup resistor
Schmitt trigger Input
Schmitt trigger input or open drain output
Three-state output
CC
.
CC
+ 2.6 volts.
A-11