TDA6651TTC1 NXP Semiconductors, TDA6651TTC1 Datasheet - Page 10

• Manufacturer Part Number: TDA6651TTC1
• Manufacturer: NXP Semiconductors

Specifications of TDA6651TTC1

• Package Type: TSSOP
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
TDA6650TT_6651TT_5
Product data sheet
8.1.1 I
8.1.2 XTOUT output buffer and mode setting
8.1.3 Step frequency setting
The device address contains programmable address bits MA1 and MA0, which offer the
possibility of having up to four MOPLL ICs in one system.
between the voltage applied to the AS input and the MA1 and MA0 bits.
Table 8.
The crystal frequency can be sent to pin XTOUT and used in the application, for example
to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of
material. To output f
is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used
to output
on, supplying the f
setting of the T[2:0] bits is given in
Table 9.
[1]
[2]
The step frequency is set by three bits, giving five steps to cope with different application
requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The
phase detector works at either 4 MHz, 2 MHz or 1 MHz.
Table 10
the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes
DB1 and DB2.
Voltage applied to pin AS
0 V to 0.1V
0.2V
0.4V
0.9V
T2
0
0
0
0
1
1
1
1
2
C-bus address selection
Automatic Loop Bandwidth Control (ALBC) is disabled at power-on reset. After power-on reset this feature
is enabled by setting T[2:0] = 011. To disable again the ALBC, set T[2:0] = 011 again. This test mode acts
like a toggle switch, which means each time it is set the status of the ALBC changes. To toggle the ALBC,
two consecutive Control byte 1s (CB1), should be sent: one byte with T[2:0] = 011 indicating that ALBC will
be switched on or off and one byte programming the test mode to be selected (see
I
This is the default mode at power-on reset. This mode disables the tuning voltage.
2
CC
CC
CC
C-bus sequence).
to 0.3V
to 0.6V
to V
shows the step frequencies and corresponding reference divider ratios. When
1
CC
2
Address selection
XTOUT buffer status and test modes
CC
f
T1
0
0
1
1
0
0
1
1
div
CC
CC
and f
or open-circuit
xtal
xtal
comp
signal. The relation between the signal on pin XTOUT and the
Rev. 05 — 10 January 2007
, it is necessary to set T[2:0] to 001. If the output signal on this pin
T0
0
1
0
1
0
1
0
1
in a test mode. At power-on, the XTOUT output buffer is set to
Pin XTOUT
disabled
f
1
f
f
1
f
disabled
Table
xtal
xtal
comp
xtal
5 V mixer/oscillator and low noise PLL synthesizer
2
2
f
f
div
div
TDA6650TT; TDA6651TT
(4 MHz)
(4 MHz)
(4 MHz)
9.
Mode
normal mode with XTOUT buffer off
normal mode with XTOUT buffer on
charge pump off
switch ALBC on or off
test mode
test mode
charge pump sinking current
charge pump sourcing current
MA1
0
0
1
1
Table 8
gives the relationship
Table
© NXP B.V. 2007. All rights reserved.
[1]
MA0
0
1
0
1
30, example of
[2]
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