C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 75

• Manufacturer Part Number: C8051T605-GSR
• Description: MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051T605-GSR

• Package: 14SOIC
• Device Core: 8051
• Family Name: C8051T60x
• Maximum Speed: 25 MHz
• Ram Size: 256 Byte
• Program Memory Size: 2 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 8
• Interface Type: I2C/SMBus/UART
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 3

15.2. Data Memory
The C8051T600/1/2/3/4/5 devices include 256 bytes of RAM, and the C8051T606 devices include 128
bytes of RAM. This memory is mapped into the internal data memory space of the 8051 controller core.
The RAM memory organization of the C8051T600/1/2/3/4/5/6 device family is shown in Figure 15.2
15.2.1. Internal RAM
The 256 bytes of internal RAM on the C8051T600/1/2/3/4/5 are mapped into the data memory space from
0x00 through 0xFF. The 128 bytes of internal RAM on the C8051T606 are mapped into the data memory
space from 0x00 through 0x7F. The 128 bytes of data memory from 0x00 to 0x7F on all devices are used
for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to
access these 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of
general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations
0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct
addressing mode.
The upper 128 bytes of data memory available on the C8051T600/1/2/3/4/5 are accessible only by indirect
addressing. This region occupies the same address space as the Special Function Registers (SFR) but is
physically separate from the SFR space. The addressing mode used by an instruction when accessing
locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space
or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect
addressing above 0x7F access the upper 128 bytes of data memory. Figure 15.2 illustrates the data mem-
ory organization of the C8051T600/1/2/3/4/5/6.
0xFF
0x7F
0x2F
0x1F
0x80
0x30
0x20
0x00
Upper 128 Bytes RAM
(Indirect Addressing)
‘T600/1/2/3/4/5 Only
(Direct and Indirect
General Purpose
Figure 15.2. RAM Memory Map
Bit Addressable
Addressing)
Registers
Rev. 1.2
(Direct Addressing)
C8051T600/1/2/3/4/5/6
Special Function
Lower 128 Bytes RAM
(Direct and Indirect
Addressing)
Registers
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