C8051T605-GSR Silicon Laboratories Inc, C8051T605-GSR Datasheet - Page 95
C8051T605-GSR
Manufacturer Part Number
C8051T605-GSR
Description
MCU 8-Bit C8051T60x 8051 CISC 2KB EPROM 1.8V/3V 14-Pin SOIC T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T600SDB.pdf
(188 pages)
Specifications of C8051T605-GSR
Package
14SOIC
Device Core
8051
Family Name
C8051T60x
Maximum Speed
25 MHz
Ram Size
256 Byte
Program Memory Size
2 KB
Operating Supply Voltage
1.8|3 V
Data Bus Width
8 Bit
Program Memory Type
EPROM
Number Of Programmable I/os
8
Interface Type
I2C/SMBus/UART
Operating Temperature
-40 to 85 °C
Number Of Timers
3
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19.7. EPROM Error Reset
If an EPROM read or write targets an illegal address, a system reset is generated. This may occur due to
any of the following:
The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf-
fected by this reset.
19.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
Programming hardware attempts to write or read an EPROM location which is above the user code
space address limit.
An EPROM read from firmware is attempted above user code space. This occurs when a MOVC
operation is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
Rev. 1.2
C8051T600/1/2/3/4/5/6
95
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