LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 39
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LPC2420FBD208-S
Manufacturer Part Number
LPC2420FBD208-S
Description
MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2460FBD208551.pdf
(79 pages)
Specifications of LPC2420FBD208-S
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Ram Size
82 KB
Operating Supply Voltage
3.3 V
Data Bus Width
16|32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
160
Interface Type
I2C/I2S/SPI/SSP/UART/USB
On-chip Adc
8-chx10-bit
On-chip Dac
1-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.22.1 Features
7.22 Watchdog timer
7.23 RTC and battery RAM
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
The RTC is a set of counters for measuring time when system power is on, and optionally
when it is off. It uses little power in Power-down and Deep power-down modes. On the
LPC2420/2460, the RTC can be clocked by a separate 32.768 kHz oscillator or by a
programmable prescale divider based on the APB clock. Also, the RTC is powered by its
own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V
supply used by the rest of the device.
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Pulse period and width can be any number of timer counts. This allows complete
flexibility in the trade-off between resolution and repetition rate. All PWM outputs will
occur at the same repetition rate.
Double edge controlled PWM outputs can be programmed to be either positive going
or negative going pulses.
Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must ‘release’ new match values before they can become
effective.
May be used as a standard timer if the PWM mode is not enabled.
A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (T
multiples of T
The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the
Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of
potential timing choices of Watchdog operation under different power reduction
conditions. It also provides the ability to run the WDT from an entirely internal source
that is not dependent on an external crystal and its associated components and
wiring, for increased reliability.
cy(WDCLK)
Rev. 05 — 24 February 2010
× 4.
cy(WDCLK)
× 256 × 4) to (T
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
cy(WDCLK)
× 2
© NXP B.V. 2010. All rights reserved.
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