SI3050-E-GTR Silicon Laboratories Inc, SI3050-E-GTR Datasheet - Page 21

• Manufacturer Part Number: SI3050-E-GTR
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3050-E-GTR

• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

When the Si3050 is in sleep mode, the PCLK signal
must remain active. In low-power sleep mode, the
Si3050 is non-functional except for the communications
link and the RGDT signal. To take the Si3050 out of
sleep mode, pulse the reset pin (RESET) low.
In summary, the powerdown/up sequence for sleep
mode is as follows:
1. Ensure the PDL bit (Register 6, bit 4) is cleared.
2. Set the PDN bit (Register 6, bit 3).
3. The device is now in sleep mode. PCLK must remain
4. To exit sleep mode, reset the Si3050 by pulsing the
5. Program registers to desired settings.
The Si3050 also supports an additional Powerdown
mode. When both the PDN (Register 6, bit 3) and PDL
(Register 6, bit 4) bits are set, the chipset enters a
complete powerdown mode and draws negligible
current (deep sleep mode). In this mode, the Si3050 is
non-functional. The RGDT pin does not function and the
Si3050 will not detect a ring. Normal operation can be
restored using the same process for taking the Si3050
out of sleep mode.
5.6. Calibration
The Si3050 initiates two auto-calibrations by default
when the device goes off-hook or experiences a loss of
line power. A 17 ms resistor calibration is performed to
allow circuitry internal to the DAA to adjust to the exact
line conditions present at the time of going off-hook.
This resistor calibration can be disabled by setting the
RCALD
calibration is also performed to remove offsets that
might be present in the on-chip A/D converter, which
could affect the A/D dynamic range. The ADC
auto-calibration is initiated after the DAA dc termination
stabilizes and the resistor calibration completes. Due to
the large variation in line conditions and line card
behavior presented to the DAA, it might be beneficial to
use manual ADC calibration instead of auto-calibration.
Manual ADC calibration should be executed as close as
possible to 256 ms before valid transmit/receive data is
expected.
The following steps should be taken to implement
manual ADC calibration:
1. The CALD bit (auto-calibration disable—Register 17)
2. The MCAL bit (manual calibration) must be toggled
3. The calibration is completed in 256 ms.
active.
RESET pin.
must be set to 1.
to one and then 0 to begin and complete the
calibration.
bit
(Register 25, bit 5).
A
256 ms
ADC
Rev. 1.11
5.7. In-Circuit Testing
The Si3050’s advanced design provides the designer
with
functionality during production line tests and support for
end-user diagnostics. Six loopback modes allow
increased coverage of system components. For four of
the test modes, a line-side power source is needed.
While a standard phone line can be used, the test circuit
in Figure 1 on page 6 is adequate. In addition, an
off-hook sequence must be performed to connect the
power source to the line-side device.
For the start-up loopback test mode, no line-side power
is necessary, and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a powerdown mode, and the system-side is in
a digital loopback mode. In this mode, data received on
DRX passes through the internal filters and is
transmitted on DTX. This path introduces approximately
0.9 dB of attenuation on the DRX signal received. The
group delay of both transmit and receive filters exists
between DRX and DTX. Clearing the PDL bit disables
this mode, and the DTX data switches to the receive
data from the line side. When the PDL bit is cleared, the
FDT bit (Register 12, bit 6) becomes active to indicate
that successful communication between the line side
and
verification that the communications link is operational.
The digital data loop-back mode offers a way to input
data on the DRX pin and have the identical data output
on the DTX pin through bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
enables this mode, which provides an easy way to verify
communication between the host processor/DSP and
the DAA. No line-side power or off-hook sequence is
required for this mode.
The remaining test modes require an off-hook sequence
to operate. The following sequence lists the off-hook
requirements:
1. Powerup or reset.
2. Allow the internal PLL to lock on PCLK and FSYNC.
3. Enable line-side by clearing PDL bit.
4. Issue an off-hook command.
5. Delay 402.75 ms for calibration to occur.
6. Set desired test mode.
The communications link digital loopback mode allows
the host processor to provide a digital input test pattern
on DRX and receive that digital test pattern back on
DTX. To enable this mode, set the IDL bit (Register 1,
bit 1). The communications link is tested in this mode.
The digital stream is delivered across the isolation
capacitors, C1 and C2, of the "2. Typical Application
system
an
increased
side
Si3050 + Si3011
is
ability
established.
to
determine
This
provides
system
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