SI3050-E-GTR Silicon Laboratories Inc, SI3050-E-GTR Datasheet - Page 37

• Manufacturer Part Number: SI3050-E-GTR
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3050-E-GTR

• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

5.33. Companding in PCM Mode
The Si3050 supports both µ-Law and A-Law companding formats in addition to 16-bit linear data. The 8-bit
companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. µ-Law
is commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected
via the PCMF bits (Register 33). Table 19 on page 38 and Table 20 on page 39 define the µ-Law and A-Law
encoding formats. If linear mode is used the resulting 16-bit data is transmitted in two consecutive 8-bit PCM
highway timeslots as shown in Figure 32.
5.34. 16 kHz Sampling Operation in PCM Mode
The Si3050 can be configured to support a 16 kHz sampling rate and transmit the data on an 8 kHz PCM or GCI
highway bus. By setting the HSSM bit (Register 7, bit 3) to 1, the DAA changes its sampling rate, Fs, to 16 kHz if it
was originally configured for an 8 kHz sampling rate. If µ-law or A-law companding is used, the resulting 8-bit
samples are transmitted in two consecutive 8-bit PCM highway timeslots. If linear mode is used, the resulting 16-bit
samples are transmitted in four consecutive 8-bit PCM highway timeslots as shown in Figure 33.
PCLK_CNT
FSYNC
PCLK
DRX
DTX
Figure 32. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
Figure 33. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
PCLK_CNT
HI-Z
0
FSYNC
PCLK
MSB
MSB
DRX
1
DTX
2
3
HI-Z
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11, HSSM = 1)
4
5
0
(TXS = RXS = 0, PHCF = 0, TRI = 1, PCMF = 11)
6
Sample 1
MSB
MSB
7
1
8
2
9
10
3
11
12
4
13
5
14
15
6
Rev. 1.11
16
17
7
18
8
19 20
9
21
10
22
Sample 2
23
11
24
12
25
Si3050 + Si3011
HI-Z
26
13
27
28
14
29
15
30
LSB
LSB
31
16
LSB
LSB
32
33
17
34
HI-Z
18
35
36 37
37