DS2153Q-A7+T&R Maxim Integrated Products, DS2153Q-A7+T&R Datasheet - Page 16

• Manufacturer Part Number: DS2153Q-A7+T&R
• Description: IC TXRX E1 1-CHIP 5V 44-PLCC
• Manufacturer: Maxim Integrated Products

Specifications of DS2153Q-A7+T&R

• Function: Single-Chip Transceiver
• Interface: E1
• Number Of Circuits: 1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 65mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
TESE
SYMBOL
TSCLKM
TCBFS
LIRST
TIRFS
TESE
ESR
—
—
TCBFS
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TIRFS
NAME AND DESCRIPTION
Transmit Elastic Store Enable.
0 = elastic store is disabled
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function
Select.
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
Elastic Stores Reset. Setting this bit from a 1 to a 0 will force
the elastic stores to a known depth. Should be toggled after
SYSCLK has been applied and is stable. Must be set and cleared
again for a subsequent reset. Do not leave this bit set high.
Line Interface Reset. Setting this bit from a 0 to a 1 will initiate
an internal reset that affects the slicer, AGC, clock recovery state
machine, and jitter attenuator. Normally this bit is only toggled
on power-up. Must be cleared and set again for a subsequent
reset.
Not Assigned. Should be set to 0 when written.
Transmit Backplane Clock Select. Must be set like RCR2.2.
0 = 1.544MHz
1 = 2.048MHz
Not Assigned. Should be set to 0 when written.
ESR
16 of 60
LIRST
—
TSCLKM
(LSB)
—