DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 56

• Manufacturer Part Number: DS3170+
• Description: IC TXRX DS3/E3 100-CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3170+

• Function: Single-Chip Transceiver
• Interface: DS3, E3
• Number Of Circuits: 1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 120mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Includes: DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -

DS3170 DS3/E3 Single-Chip Transceiver
10.2.1.1.1 LIU Enabled, Loop Timing Enabled
In this mode, the receive LIU sources the clock for both the receive and transmit logic. The RCLKO, TCLKO and
TLCLK clock output pins will be the same. The transmit or receive line payload signal pins can be timed to any of
these clock. The use of the RCLKO pin as the timing source is suggested. If RCLKO is used as the timing source,
be sure to set PORT.CR3.RFTS = 0 for output timing.
10.2.1.1.2 LIU Disabled, Loop Timing Enabled
In this mode, the RLCLK pin are the source of the clock for both the receive and transmit logic. The RCLKO,
TCLKO and TLCLK clock output pins will both be the same as the RLCLK clock. The transmit or receive line
payload signals can be timed to any of these clock pins. The use of the RLCLK pin as the timing source is
suggested. If RLCLK is used as the timing source, be sure to set PORT.CR3.RFTS = 1 for input timing.
10.2.1.2 Loop Timing Disabled
When loop timing is disabled, the transmit clock source can be different than the receive clock source. The
loopback functions, LLB, PLB and DLB, will cause the clock sources to switch when they are activated. Care must
be taken when selecting the clock reference for the transmit and receive signals.
The most versatile clocking option has the receive line interface signals timed to RLCLK, the transmit line interface
signals timed to TLCLK, the receive framer signals timed to RCLKO, and the transmit framer signals timed to
TCLKO. This clocking arrangement works in all modes.
When LLB is enabled, the clock on the TLCLK pin will switch to the clock from the RLCLK pin or RX LIU. It is
recommended that the transmit line interface signals be timed to the TLCLK pins. If TLCLK is used as the timing
source, be sure to set PORT.CR3.TLTS = 0 for output timing.
When PLB is enabled, the TCLKI pin will not be used and the internal transmit clock is switched to the internal
receive clock. The clock on the TCLKO pin will switch to the clock from the RLCLK pins or RX LIU. The framer
input signals will be ignored while PLB is enabled. It is recommended that the transmit line interface signals be
timed to the TCLKO pins.
When DLB is enabled, the internal receive clock is switched to the internal transmit clock which is sourced from the
TCLKI pin or one of the CLAD clocks, and the clock on the RLCLK pin or from the RX LIU will not be used. The
clock on the RCLKO pin will switch to the clock on the TCLKI pins or one of the CLAD clocks. The receive line
signals from the RX LIU or line interface pins will be ignored. It is recommended that the receive framer pins be
timed to the RCLKO pin. If TCLKO is used as the timing source, be sure to set PORT.CR3.TFTS = 0 for output
timing.
When both DLB and LLB are enabled, the TLCLK clock pin are connected to either the RX LIU recovered clock or
the RLCLK clock pin, and the RCLKO clock pin will be connected to the TCLKI clock pin or one of the CLAD
clocks. It is recommended that the transmit line signals be timed to the TLCLK pin, the receive line interface signals
be timed to the RLCLK pin, the receive framer signals be timed to the RCLKO pin, and the transmit framer signals
be timed to the TCLKO pin.
10.2.1.2.1 LIU Enabled - CLAD Timing Disabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
10.2.1.2.2 LIU Enabled - CLAD Timing Enabled – no LB
In this mode, the receive LIU sources the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
10.2.1.2.3 LIU Disabled - CLAD Timing Disabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and the TCLKI pin sources the clock for the
transmit logic.
10.2.1.2.4 LIU Disabled - CLAD Timing Enabled – no LB
In this mode, the RLCLK pin source the clock for the receive logic and one of the CLAD clocks sources the clock
for the transmit logic.
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