PEB20320H-V34 Infineon Technologies, PEB20320H-V34 Datasheet - Page 83

• Manufacturer Part Number: PEB20320H-V34
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34; PEB20320H-V34IN

7. For frames not fulfilling check a) no data are transferred to the shared memory
8. The check is reported in the RA bit in the last receive descriptor of the frame
Options
The different options for this mode are:
– The kind of Frame Check Sequence (FCS)
– the transfer of the FCS together with the received data is programmable by the CS bit.
Interrupts
The possible interrupts for the mode in receive direction are:
HI:
FI:
IFC: issued if a change of the interframe time-fill state as discussed in 2. has occurred.
SF:
User’s Manual
irrespective of CS.
Only an interrupt with the bit FI, SF and (possibly) ERR is generated.
For frames fulfilling check a) but not check b) data is transferred to the shared memory
but the SF bit in the last receive descriptor is set.
RA = 1: The frame was stopped by the sequence 7F
RA = 0: The frame was not stopped by the sequence 7F
Note: A receive descriptor with RA = 1 may also result from a fast receive abort or a
Two kinds of FCS are implemented and can be chosen by CRC bit.
CRC = 0: the generator polynomial x
CCITT Q.921)
CRC = 1: the generator polynomial
x
used.
CS = 0: FCS is not transferred to the data section
CS = 1: FCS is transferred to the data section.
Note: FCS is always checked irrespective of the CS bit.
32
+ x
issued if the HI bit is detected in the receive descriptor (not maskable)
issued if a received frame has been finished as discussed in 1.b of the protocol
features (also for frames which do not lead to data transfer as discussed in 7. of the
protocol features)
(maskable by FIR in the channel spec.)
(maskable by IFC in the channel spec.)
a frame not fulfilling check a) has been detected (maskable by SFE in the
channel spec.)
receive abort channel command or from a receive descriptor with set HOLD bit.
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
16
83
+ x
8
+ x
12
+ x
7
+ x
5
+ 1 is used (2 byte FCS of
5
H
+ x
H
4
.
+ x
Functional Description
2
+ x + 1 (4 byte FCS) is
PEB 20320
01.2000