PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 134

• Manufacturer Part Number: PEF 20550 H V2.1
• Description: IC INTERFACE CTRLR PCM MQFP80
• Manufacturer: Infineon Technologies
• Series: ELIC®r

Specifications of PEF 20550 H V2.1

• Function: Line Card Controller
• Interface: ISDN, PCM
• Number Of Circuits: 1
• Voltage - Supply: 5V
• Current - Supply: 15mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-SQFP
• Includes: Change Detection, Power-Up Reset Generation
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Other names: PEF20550HV2.1XT; PEF20550HV21XP; SP000007794; SP000007795

DRCS
OFD1..0
DRE
ADSRO
4.6.5
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Note: If both DRCS and ADSRO are set to logical 1, the PCM-output data are delayed
OFU1..0
URE
Note: If EMOD:ECMD2 is set to ’0’ some restrictions apply to the setting of PCSR
Semiconductor Group
bit 7
DRCS
by two PDC-clock cycles.
DRCS and ADSRO were added to the standard EPIC-1 PCSR register
implemented in the PEB 2055 up to and including version A3.
(see chapter 4.5).
PCM-Clock Shift Register (PCSR)
Double Rate Clock Shift.
0…the PCM-input and output data are not delayed
1…the PCM-input and output data are delayed by one PDC-clock cycle
Offset Downstream bits 1…0, see POFD-register.
Downstream Rising Edge.
0…the PCM-data is sampled with the falling edge of PDC
1…the PCM-data is sampled with the rising edge of PDC
Add Shift Register on Output.
0…the PCM-output data are not delayed
1…the PCM-output data are delayed by one PDC-clock cycle
Offset Upstream bits 1…0, see POFU-register.
Upstream Rising Edge.
0…the PCM-data is transmitted with the falling edge of PDC
1…the PCM-data is transmitted with the rising edge of PDC
OFD1
H
OFD0
DRE
134
ADSRO
read/write
read/write
Detailed Register Description
OFU1
address: 14
address: 28
OFU0
PEB 20550
PEF 20550
bit 0
H
H
URE
01.96