PEF 20550 H V2.1 Infineon Technologies, PEF 20550 H V2.1 Datasheet - Page 257
PEF 20550 H V2.1
Manufacturer Part Number
PEF 20550 H V2.1
Description
IC INTERFACE CTRLR PCM MQFP80
Manufacturer
Infineon Technologies
Series
ELIC®r
Datasheet
1.PEF_20550_H_V2.1.pdf
(407 pages)
Specifications of PEF 20550 H V2.1
Function
Line Card Controller
Interface
ISDN, PCM
Number Of Circuits
1
Voltage - Supply
5V
Current - Supply
15mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
80-SQFP
Includes
Change Detection, Power-Up Reset Generation
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Other names
PEF20550HV2.1XT
PEF20550HV21XP
SP000007794
SP000007795
PEF20550HV21XP
SP000007794
SP000007795
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Tristate Behavior at the Configurable Interface
The downstream control memory code field, together with the CSCR and OMDR
registers also defines the state of the output driver at the downstream CFI ports.
Unassigned channels (code ‘0000’) are set to the inactive state. Subchannels (codes
‘0010’ to ‘0111’) are only active during the sub-timeslot position specified in CSCR. The
OMDR:COS bit selects between tristate outputs and open drain outputs:
Table 41
Tristate/Open Drain Output Characteristics at the CFI
Logical State
Logical 0
Logical 1
Inactive
1)
Figure 91 illustrates this behavior in case of tristate outputs:
Figure 91
Tristate Behavior at the CFI
Semiconductor Group
An external pull-up resistor is required to establish a high voltage level.
CFI Time-Slot #
CM Data Field
CM Code Field
DD #
High Z
1 -
0 -
X X X X X X X X
0
Unassigned
Channel
0
N
0
Tristate Outputs
Low voltage level
High voltage level
High impedance
0
(Switched from PCM)
64 kbps Channel
0
Pointer to DM
0
N+1
257
0
1
CSCR : SC#1..#0 = 01
(Switched from PCM)
16 kbps Channel
0
Pointer to DM
1
N+2
1
Open Drain Outputs
Low voltage level
Not driven
Not driven
0
1
µP Channel
(Always 64 kbit/s)
1
0
Application Hints
1)
1)
1
0
N+3
1
0
0
PEB 20550
PEF 20550
0
ITD08070
1
1
0
01.96
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