PEF 82912 F V1.4 Infineon Technologies, PEF 82912 F V1.4 Datasheet
PEF 82912 F V1.4
Specifications of PEF 82912 F V1.4
PEF82912FV14XP
SP000007558
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PEF 82912 F V1.4 Summary of contents
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Q-SMINT I 2B1Q Second Gen. Modular ISDN NT (Intelligent) PEF 82912/82913 Version 1.3 Wir ed Communications ...
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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Q-SMINT I 2B1Q Second Gen. Modular ISDN NT (Intelligent) PEF 82912/82913 Version 1.3 Wir ed Communications ...
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... Reset value of MASKU is FF Chapter 7.3 External circuitry for T-SMINT updated For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com March 2001 Preliminary Data Sheet 10.00 ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.2.3 Availability of Maintenance Channel Information . . . . . . . . . . . . . . . . 64 2.4.2.4 M-Bit Register Access Timing . . . . . . . . . ...
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Table of Contents 3.1.2 Complete Activation Initiated 121 3.1.3 Complete Activation ...
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Table of Contents 4.8.2 MASK - Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 4.11.16 NEBE - Near End Block Error Counter Register . . . . . . . . . . . . . . . . . 191 4.11.17 ISTAU - Interrupt Status Register U-Interface . . . ...
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List of Figures Figure 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 42 M4, M5, M6 Bit Control in Receive Direction . . . . . . . . . . . . . . . . . . . . 78 Figure 43 M4, M5, M6 Bit ...
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List of Figures Figure 83 Microprocessor Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 ...
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List of Tables Table 1 NT Products of the 2nd Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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List of Tables Table 43 Related Documents to the U-Interface 212 Table 44 C/I Codes . . ...
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Overview The PEF 82912 / 82913 (Q-SMINT 2 interface. A microcontroller interface provides access to both transceivers as well as the IOM -2 interface. However, as opposed to its bigger brother Q-SMINT an HDLC controller. Main target applications of ...
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... V1.1, Data Sheet 10.97, Siemens AG, 1997 [13] IOM -2 Interface Reference Guide, Siemens AG, 03.91 [14] SCOUT-S(X), Siemens Codec with S/T-Transceiver, PSB 2138x V1.3, Preliminary Data Sheet 8.99, Infineon Technologies, 1999 [15] PITA, PCI Interface for Telephony/Data Applications V0.3, SICAN GmbH, September 1997 [16] Dual Channel SLICOFI-2, HV-SLIC; DUSLIC; PEB3265, 4265, 4266; Data Sheet DS2, Infineon Technologies, July 2000 ...
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Second Gen. Modular ISDN NT (Intelligent) ® Q-SMINT I Version 1.3 1.2 Features PEF 82912 Features known from the PEB/PEF 8191 • U-transceiver and S-transceiver on one chip • Perfectly suited for high-end intelligent NTs that require multiple ...
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New Features • Reduced number of external components for external U-hybrid required • Optional use 2x20 • Pin Uref and the according external capacitor removed • Improved ESD (2 kV instead of <850 V) • Inputs ...
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Not Supported are ... • Integrated U-hybrid • On-chip HDLC controller • ’Self test request’ and ’Self test passed’ of U-transceiver • TE-mode of the S-transceiver • DECT-link capability • SRA (capacitive receiver coupling is not suited for S-feeding). ...
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Pin Configuration • /VDDDET 49 50 VDDa_SR 51 52 VSSa_SR PS1 XOUT 59 XIN 60 ...
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Block Diagram • SR1 SR2 SX1 S-Transceiver SX2 to µP IF TP1 Factory Tests TP2 IOM-2 Interface FSC DCL BCL DU DD Figure 2 Block Diagram Data Sheet XIN XOUT VDDDET Clock Generation POR/UVD D-Channel Arbitration ...
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Pin Definitions and Functions • Table 2 Pin Definitions and Functions Pin Symbol 2 VDDa_UR 1 VSSa_UR 62 VDDa_UX 63 VSSa_UX 51 VDDa_SR 52 VSSa_SR 46 VDDa_SX 45 VSSa_SX 29 VDDD 30 VSSD 13 VDDD 14 VSSD 32 FSC ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 8 SDS1 7 SDS2 SCLK 26 AD5 27 SDR 27 AD6 Data Sheet Type Function O Serial Data Strobe1: Programmable strobe signal for time slot and/ or D-channel ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 28 SDX 28 AD7 21 AD0 22 AD1 23 AD2 24 AD3 25 AD4 ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 10 WR R/W 9 ALE 5 RST 6 RSTO 15 INT 18 MCLK 19 20 EAW 43 SX1 44 SX2 47 SR1 Data Sheet Type Function I Write Indicates a write ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 48 SR2 60 XIN 59 XOUT 64 AOUT 61 BOUT 3 AIN 4 BIN 49 VDDDET 16 MTI 55 PS1 41 PS2 17 ACT 42 TP1 Data Sheet Type Function I ...
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Table 2 Pin Definitions and Functions (cont’d) Pin Symbol 50 TP2 56, 57, res 58 1) This function of pin EAW is different to that defined in Ref. [14] I: Input O: Output (Push-Pull) OD: Output (Open Drain) 1.7.1 Specific ...
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Test Modes The test patterns on the S-interface (‘2 kHz Single Pulses‘, ‘96 kHz Continuous Pulses‘) and on the U-interface (‘Data Through‘, ‘Send Single Pulses‘) are invoked via C/I codes (TM1, TM2, DT, SSP). Setting SRES.RES_U to ‘1‘ forces the ...
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IOM-2 Slave e.g. SLICOFI-2 Figure 4 Control via µP Interface Alternatively, the Q-SMINT I can be controlled via b) the IOM -2 Interface - Access of on-chip registers via the Monitor channel with Header/Address/Data format (Device is Monitor slave) ...
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S IOM -2 IOM-2 Master e.g. UTAH Figure 5 Control via IOM -2 Interface Data Sheet C/I1 C/I0 MON INT 16 PEF 82912/82913 Overview U Register iomslave.vsd 2001-03-30 ...
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Functional Description 2.1 Microcontroller Interfaces The Q-SMINT I supports either a serial or a parallel microcontroller interface. For applications where no controller is connected to the Q-SMINT I microcontroller interface, register programming is done via the IOM -2 MONITOR ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola and to the Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data is transferred ...
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Write Access CS SCLK SDR SDX Read Access CS SCLK SDR SDX Figure 6 Serial Control Interface Timing Data Sheet Command/Address Header ...
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Programming Sequences The basic structure of a read/write access to the Q-SMINT I registers via the serial control interface is shown in • write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 7 Serial Command Structure ...
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Header 40 : Non-interleaved A-D-A-D Sequences H The non-interleaved A-D-A-D sequences give direct read/write access to the address range 00 -7F and can have any length. In this mode SDX and SDR can be connected H H together allowing data ...
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Header 41 : Non-interleaved A-D-D-D Sequence H This sequence (header 41 interleaved A-D-A-D read access. Generally, it can be used for any register access to the address range 20 - the wradr. The sequence can have any length ...
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Note: For a selected interface mode which does not require all pins (e.g. address pins) the unused pins must be tied read/write access to the Q-SMINT I registers can be done in multiplexed or non- multiplexed mode. ...
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Direct Address Mode AMOD = ´1´ 7Fh 7Eh 7Dh 7Ch 04h 03h 02h 01h 00h Figure 8 Direct/Indirect Register Address Mode 2.1.3 Microcontroller Clock Generation The microcontroller clock is derived from the unregulated 15.36 MHz clock ...
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Reset Generation Figure 9 shows the organization of the reset generation of the Q-SMINT I. •. 125µs C/I0 Code Change (Exchange Awake 125µs Watchdog Software Reset Register (SRES) RES_CI Reset RES_HDLC Functional Block RES_S RES_U Internal Reset ...
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The internal reset sources set the MODE1 register to its reset value. Table 8 Reset Source Selection RSS2 RSS1 Bit 1 Bit POR/UVD can be enabled/disabled via pin VDDDET • ...
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External Reset Input At the RST input an external reset can be applied forcing the Q-SMINT I in the reset state. This external reset signal is additionally fed to the RSTO output. After release of an external reset, the C ...
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IOM -2 Interface The Q-SMINT I supports the IOM -2 interface in terminal mode (DCL=1.536 MHz) according to the IOM -2 Reference Guide [13]. 2.3.1 IOM -2 Functional Description The IOM -2 interface consists of four lines: FSC, DCL, ...
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The frame is composed of three channels • Channel 0 contains 144-kbit/s of user and signaling data (2B + D), a MONITOR programming channel (MON0) and a command/indication channel (CI0) for control and programming of e.g. the U-transceiver. • Channel ...
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Figure 11 Architecture of the IOM -2 Handler Data Sheet PEF 82912/82913 Functional Description CDA Data Monitor Data TIC Bus Data C/I0 Data C/I1 Data D/B1/B2 Data C/I0 Data FSC DCL BCL/SCLK SDS1 SDS2 2001-03-30 ...
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Controller Data Access (CDA) The four controller data access registers (CDA10, CDA11, CDA20, CDA21) provide microcontroller access to the 12 IOM -2 time slots and more: • looping four independent PCM channels from ...
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TSa 1 0 Enable output (EN_O0) CDAx0 1 0 TSa a,b = 0...11 Figure 12 Data Access via CDAx0 and CDAx1 register pairs Looping and Shifting Data Figure 13 gives examples for typical configurations ...
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Looping Data .TSS: .DPS .SWAP b) Shifting Data TSa CDA10 .TSS: TSa .DPS .SWAP c) Switching Data TSa CDA10 .TSS: TSa .DPS .SWAP Figure 13 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting (Switching) ...
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Figure 14 shows the timing of looping TSa from via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD. Figure 15 shows the timing of shifting data ...
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Shifting TSa TSb within one frame (a,b: 0...11 and b a+2) FSC DU TSa (DD) CDAxy b) Shifting TSa TSb in the next frame (a,b: 0...11 and ( <a) FSC DU TSa (DD) CDAxy ...
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Monitoring Data Figure 16 gives an example for monitoring of two IOM -2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots ...
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Monitoring TIC Bus Monitoring the TIC bus (TS11) is handled as a special case. The TIC bus can be monitored with the registers CDAx0 by setting the EN_TBM (Enable TIC Bus Monitoring) bit in the control registers CRx. The TSDPx0 ...
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Table 9 Examples for Synchronous Transfer Interrupts Enabled Interrupts (Register MSTI) STI STOV ...
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INT CIC CIC 1 0 WOV WOV S S MOS MOS 1 0 MASK ISTA Figure 17 Interrupt Structure of the Synchronous Data Transfer Figure 18 shows some examples based on the timeslot structure. Figure ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Serial Data Strobe Signal For time slot oriented standard devices at the IOM -2 interface, the Q-SMINT I provides two independent data strobe signals SDS1 and SDS2. The two strobe signals can be generated with every 8-kHz-frame and are ...
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Figure 19 shows three examples for the generation of a strobe signal. In example 1 the SDS is active during channel B2 on IOM -2, whereas in the second example during IC2 and MON1. The third example shows a strobe ...
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The MONITOR channel protocol is described In the following section and shall illustrate this. The relevant control and status bits for transmission and reception are listed in Table 10 and Table 10 Transmit Direction Control/ Register Status Bit Control MOCR ...
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P µ MIE = 1 MOX = ADR MXC = 1 MAC = 1 MDA Int. MOX = DATA1 MDA Int. MOX = DATA2 MDA Int. MXC = 0 MAC = 0 Figure 20 MONITOR Channel Protocol (IOM Before ...
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In addition, it enables other MONITOR channel interrupts by setting MONITOR Interrupt Enable (MIE) to ’1’ result, the first MONITOR byte is acknowledged by the receiving device setting the MR bit to ’0’. This causes a MONITOR Data ...
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Since a double last-look criterion is implemented the receiver is able to receive the MON slot data at least twice (in two consecutive frames), the receiver waits for the acknowledge of the reception of two identical bytes in two ...
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IOM -2 Frame No. MX (DU) MR (DD) Figure 21 Monitor Channel, Transmission Abort requested by the Receiver • IOM -2 Frame No. MR (DU) MX (DD) Figure 22 Monitor Channel, Transmission Abort requested by the Transmitter • IOM ...
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MONITOR Channel Programming as a Master Device The master mode is selected by default if one of the microcontroller interfaces is selected. The monitor data is written by the microcontroller in the MOX register and transmitted via IOM -2 ...
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DU 1st byte value DU 2nd byte value DU 3rd byte value DU 4th byte value DU (nth + 3) byte value All registers can be read back when setting the R/W bit to ’1’. The Q-SMINT I responds ...
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MASK U ST CIC 1 WOV S MOS 1 INT Figure 24 MONITOR Interrupt Structure 2.3.4 C/I Channel Handling The Command/Indication channel carries real-time status information between the Q- SMINT I and another device connected to the IOM -2. ...
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In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits are read whereby only the 4 LSBs are used for comparison and interrupt generation (i.e. the higher two bits are ignored). The ...
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D-Channel Access Control The upstream D-channel is arbitrated between the S-bus and external HDLC controllers via the TIC bus (S/G, BAC, TBA bits) according to the IOM -2 Reference Guide Further to the implementation in the INTC ...
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Q-SMINT I E-Bit S D Figure 27 D-Channel Arbitration: C with HDLC and no Access to TIC Bus 2.3.5.2 TIC Bus Handling The TIC bus is implemented to organize the access to the C/I0-channel and to the D- channel ...
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Figure 28 Structure of Last Octet of Ch2 on DU When the TIC bus is seized by the Q-SMINT I, the bus is identified to other devices as occupied via the DU Ch2 Bus Accessed-bit state ...
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MON Figure 29 Structure of Last Octet of Ch2 on DD 2.3.5.4 D-Channel Arbitration In intelligent NT applications (selected via register S_MODE.MODE2-0) the Q-SMINT I has to share the upstream D-channel with one or more ...
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Table 12 Q-SMINT I Configuration Settings in Intelligent NT Applications Functional Configuration Block Description Layer 1 Select Intelligent NT mode Layer 2 Enable S/G bit and TIC bus evaluation Note: For mode selection in the S_MODE register the MODE1/2 ...
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D=0) & [BAC = 1 or (BAC = 0 & CNT BAC = d.c. DCI = 0 S ACCESS 1) S Setting DCI = 1 causes ...
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Local D-Channel Controller Transmits Upstream In the initial state (’Ready’ state) neither the local D-channel sources nor any of the terminals connected to the S-bus transmit in the D-channel. The Q-SMINT I S-transceiver thus receives BAC = “1” (IOM ...
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Activation/Deactivation of IOM The deactivation procedure of the IOM -2 interface is shown in Figure 31. After detecting the code DI (Deactivation Indication) the Q-SMINT I responds by transmitting DC (Deactivation Confirmation) during subsequent frames and stops the timing ...
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A deactivated IOM -2 can be reactivated by one of the following methods: • Pulling pin DU line low: – directly at the IOM -2 interface – via the µP interface with "Software Power Up" (IOM_CR:SPU bit) • Pulling pin ...
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SW (Inverted) Synch Word 18 Bit (9 Quat) <---1,5 ms---> Figure 33 U-Basic Frame Structure Out of the 222 information bits 216 contain data from 12 IOM remaining 6 bits are used to transmit ...
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Table 14 U-Superframe Format (cont’d) Fram- ing 2,3… – ISW Inverted Synchronization Word (quad): – SW Synchronization Word (quad): – CRC Cyclic Redundancy Check – EOC Embedded Operation Channel – ACT Activation bit – DEA Deactivation ...
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Tone/Pulse Patterns nc/Inv 2B1Q Encoding Figure 34 U Framer - Data Flow Scheme 2B1Q • U -Deframer 2B1Q (M-bit handling acc. to ETR080 2B1Q Decoding Figure 35 U ...
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Maintenance Channel The last three symbols (6 bits) of each basic frame are used as M (Maintenance)- channel for the exchange of operation and maintenance data between the network and the NT. Approved M-bit data is first processed and ...
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Table 15 Enabling the Maintenance Channel (Receive Direction) Pend. Deac. S/T Pend. Deac. U Analog Loop Back Reporting and execution of maintenance information is only sensible if the Q-SMINT I is synchronous. Filters are provided to avoid meaningless reporting. Reset ...
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Interrupt #1 Frame No. max. 3 Base Frames 12ms Interrupt #1 Frame No. Figure 36 Write Access Timing The read access timing is illustrated in name is associated with each read register (EOCR, M4R, M56R). An EOC interrupt ...
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EOC Interrupt #1 Frame No. µC read access time max. 3 Base Frames set active in frame #1 if value has been updated M4 Interrupt #1 Frame ...
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The data/message indicator needs to be set to (1) to indicate that the information field contains a message. If set to (0), numerical data is transferred to the NT. Currently no numerical data transfer to or from the NT is ...
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Table 17 Usage of Supported EOC-Commands(cont’d) Hex- Function code i1- LB1 Closes B1 loop-back in NT. All B1-channel data will be looped back within the Q-SMINT I U-transceiver. The bits LB1 and U/IOM are set in the ...
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MFILT.EOC EOCR Register Processor Figure 38 EOC Message Reception • EOCW Figure 39 EOC Command/Message Transmission Data Sheet U Receive Superframe EOC Message Filtering Last Verified EOC Message EOC Echo U-Rx Frame Processor µC EOC Command/ Message every 6 ...
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EOC Operating Modes The EOC operating modes are programmable in the MFILT register (see Chapter 4.11.2) EOC Auto Mode – Acknowledgement: All received EOC-frames are echoed back to the exchange immediately without triple-last-look address other than (000) ...
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Transparent mode with ’On Change bit’ active – Acknowledgment: There is no automatic acknowledgement in transparent mode. For details see above. – Latching: No latching is performed due to no execution. – Reporting: This mode is almost identical to the ...
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EOC Automode Table 18 EOC Auto Mode remarks input from µC Access to EOCW register has direct impact on EOC TX. EOC EOC ...
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Transparent mode 6 ms) Table 19 Transparent mode 6 ms remarks input from µC EOC TX EOC RX report to µC Transparent mode ’@change’ Table 20 Transparent mode ’@change’ remarks input from µC EOC TX EOC RX report to µC ...
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Processing of the Overhead Bits M4, M5, M6 2.4.4.1 M4 Bit Reporting to the µC Four different validation modes can be selected and take effect on a per bit base. Only if the received M4 bit change has been ...
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M4 M5, M6 Figure 40 Maintenance Channel Filtering Options Figure 41 illustrates the point of time when a detected M4, M5, M6 bit change is reported to the µC and when it is reported to the state machine: • ...
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However, if the same filter is selected towards the state machine as programmed towards the µC, the user has to be aware that if CRC mode is active, the state machine is informed at the end of the next U-superframe. ...
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MFILT.M4 M4R Register UOA DEA ACT AIB EN/ DIS '1' MUX M4WMASK.Bit6 State Machine Figure 42 M4, M5, M6 Bit Control in Receive Direction • M4W Register NIB SAI M46 '1' M4WMASK MUX MUX '1'= M4W Reg. '0'= SM/ ...
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Cyclic Redundancy Check / FEBE bit An error monitoring function is implemented covering the and M4 data transmission of a U-superframe by a Cyclic Redundancy Check (CRC). The computed polynomial is: The check digits (CRC bits ...
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IOM -2 DD CRCOK=0 INT µC access DU µC access INT *0.0625 of a SFR is the 60 Quats offset of the NT transmit data. Figure 44 CRC-Process Data Sheet NT U (2B + D), M4 SFR(n) G(u) ...
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Block Error Counters The U-transceiver provides internal counters for far-end and near-end block errors. This allows a comfortable surveillance of the transmission quality at the U-interface. In addition, the occurrence of near-end errors, far-end errors, and the simultaneous occurrence ...
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EOC Command RCC: Requests the Q-SMINT I to send corrupt CRCs. After issuing RCC near-end block errors will be registered on the LT-side. The functional behavior of the Q-SMINT I and the FEBE-counter depends on the mode selected: – ...
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EOC µC Interface Transparent ISTAU.EOC=1 EOCR = 'NCC' ISTAU.FEBE/ ERROR COUNT NEBE=1 NEBE M56R.NEBE = '1' ISTAU.EOC=1 EOCR = 'RTN' ISTAU.EOC=1 EOCR = 'RCC' TEST.CCRC = '1' ERROR ISTAU.FEBE/ COUNT NEBE=1 FEBE M56R.FEBE = '1' ISTAU.EOC=1 EOCR = 'RTN' ...
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Table 22 presents all defined C/I codes. A new command or indication will be recognized as valid after it has been detected in two successive IOM criterion). Note: Unconditional C/I-Commands must be applied for at least 4 IOM -2 frames ...
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DC: Deactivation Confirmation DI: Deactivation Indication DR: Deactivation Request DT: Data Through test mode EI1: Error Indication 1 PU: Power-Up RES: Reset SSP: Send Single Pulses test mode TIM: Timing request 2.4.10 State Machines for Line Activation / Deactivation 2.4.10.1 ...
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Figure 46 shows how to interpret the state diagrams. • Figure 46 Explanation of State Diagram Notation Combinations of transition criteria are possible. Logical “AND” is indicated by “&” (TN & DC), logical “OR” is written “or” and for a ...
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Standard NT State Machine (IEC-Q / NTC-Q Compatible) • SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' T12S SN1 EC-Training AL ...
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Note: The test modes ‘Data Through‘ (DT) and ‘Send Single Pulses‘ (SSP) are invoked via C/I codes ’DT’ and ’SSP’ according to forces the U-transceiver into test mode ‘Quiet Mode‘ (QM), i.e. the U-transceiver is hardware reset. If the Metallic ...
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TIM Timing The U-transceiver is requested to enter state ’IOM -2 Awaked’. U-Interface Events: ACT = 0/1 ACT-bit received from LT-side. – ACT = 1 requests the U-transceiver to transmit transparently in both directions. In the case of loop-backs, however, ...
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C/I-Indications AI Activation Indication The U-transceiver has established transparency of transmission. The downstream device is requested to establish layer-1 functionality. AIL Activation Indication Loopback The U-transceiver has established transparency of transmission. The downstream device is requested to establish a loopback ...
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Note: Alternating ± 3 symbols at 10 kHz. 2) Note: 4 Options for the test signal can be selected by register TEST kHz signal composed by alternating +/-3 or +/-1 transmit pulses. A series of single pulses ...
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Signals on IOM -2 The Data (B+B+D) is set to all ’1’s in all states besides the states listed in Dependence of Outputs 1) • Outputs denoted with Signal output on U depends on the received EOC command and on ...
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Description of the NT-States The following states are used: Alerting The wake-up signal TN is transmitted for a period of T11 either in response to a received wake-up signal start an activation procedure on the LT-side. ...
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Error S/T The downstream device error condition (EI1). The LT-side is informed by setting the ACT-bit to “0” (loss of transparency on the NT-side). IOM -2-Awaked The U-transceiver is deactivated, but may not enter the power-down mode. ...
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Synchronized 2 In this state the U-transceiver has received UOA = 1. This is a request to activate the downstream device. Test The test signal SP is issued as long as C/I=SSP is applied. For further details see Table 24. ...
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C/I changes at irrelevant state transitions are omitted, hence the number of interrupts is reduced. All advantages can be offered by the following minor changes to the existing state machine: • Table 27 Changes to achieve Simplified NT ...
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Table 27 Changes to achieve Simplified NT State Machine(cont’d) Change Not Supported State Transitions Data Sheet State Standard NT State Machine Test to IOM -2 none Awaked Reset to Alerting DI & NTAUTO all other no changes transitions 97 PEF ...
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SN0 T14S Pending Timing DC Any State T14S DI SSP or SP C/I= 'SSP' Test DR TIM SN0 Reset Any State DR Pin-RST or ARL C/I= 'RES' T12S SN1 EC-Training AL DR LSEC or T12E act=0 SN3 Wait for ...
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Table 28 Appearance of the State Machine to the Software C/I ind. Meaning DR LT has decided to deactivate or activation was lost: – after an activation or – after an activation attempt or – after reset ® DC ...
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A test mode is valid for 75 seconds. If during the 75 seconds a valid pulse sequence is detected the 75 s timer starts again. After expiry of the 75 s timer the MLT maintenance controller goes back to normal ...
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U-Transceiver Interrupt Structure The U-Interrupt Status register (ISTAU) contains the interrupt sources of the U- Transceiver (Figure 50). Each source can be masked by setting the corresponding bit of the U-Interrupt Mask register (MASKU) to ’1’. Such masked interrupt ...
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M56R 7 0 OPMODE.MLT MS2 MS1 + NEBE MFILT M61 CRC, TLL, M52 no Filtering M51 0 FEBE M4R MFILT 7 AIB UOA M46 CRC, TLL, M45 no M44 Filtering SCO DEA 0 ACT EOCR MFILT 15 TLL, CHG, ...
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S-Transceiver The S-Transceiver offers the NT and LT-S mode state machines described in the User’s Manual V3.4 [10]. The S-transceiver lies in IOM -2 channel 1 (default) and is configured and controlled via the registers described in but can ...
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Figure 52 Frame Structure at Reference Points S and T (ITU I.430) – F Framing Bit – L. D.C. Balancing Bit – D D-Channel Data Bit – E D-Channel Echo Bit – F Auxiliary Framing Bit A – N ...
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S/Q Channels, Multiframing According to ITU recommendation I.430 a multi-frame provides extra layer-1 capacity in the TE-to-NT direction through the use of an extra channel between the TE and NT (Q- channel). The Q bits are defined to be ...
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The S-transceiver starts multiframing if SQXR1.MFEN is set. After multi-frame synchronization has been established in the TE, the Q data will be inserted at the upstream (TE S data will be inserted at the downstream (NT (see Table 30). Access ...
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C/I Command IOM-2 C/I Indication Figure 53 S-Transceiver Control The state diagram notation is given in The information contained in the state diagrams are: – state name – Signal received from the line interface (INFO) – Signal transmitted to ...
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IOM-2 Interface C/I code S/T Interface INFO Figure 54 State Diagram Notation As can be seen from the transition criteria, combinations of multiple conditions are possible as well. A “ ” stands for a logical AND combination. And a ...
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C/I Codes in Reset State In the reset state the C/I code 0000 (TIM) is issued. This state is entered either after a hardware reset (RST) or with the C/I code RES. C/I Codes in Deactivated State If the S-transceiver ...
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Receive Infos on S/T I0 INFO 0 detected I0 Level detected (signal different to I0) I3 INFO 3 detected I3 Any INFO other than INFO 3 Transmit Infos on S/T I0 INFO 0 I2 INFO 2 I4 INFO 4 It ...
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State Machine NT Mode • RST TIM RES DR Reset i0 * RES DC Any State AID RSY ARD i3*ARD G2 Lost Framing S/T i3*AID i2 i3 RSY DR ARD 2) AID RSY RSY G3 Lost Framing U i2 ...
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G1 Deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM -2 interface ...
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G4 wait for DR Final state after a deactivation request. The S-transceiver remains in this state until DC is issued. Unconditional States Test Mode TM1 Send Single Pulses Test Mode TM2 Send Continuous Pulses C/I Commands • Command Abbr. Deactivation ...
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Command Abbr. Activation Indication AIL Loop Deactivation DC Confirmation Indication Abbr. Timing TIM Receiver not RSY Synchronous Activation Request AR Illegal Code Ciolation CVR Activation Indication AI Deactivation DI Indication Data Sheet Code Remark 1110 Activation Indication Loop 1111 Deactivation ...
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State Machine LT-S Mode • RST TIM RES DR Reset i0 * RES DC Any State DC RSY ARD i3 G2 Lost Framing S ARD = AR or ARL Figure 56 State Machine LT-S ...
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G1 deactivated The S-transceiver is not transmitting. There is no signal detected on the S/T-interface, and no activation command is received in the C/I channel. Activation is possible from the S/T interface and from the IOM -2 interface. G2 pending ...
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Test mode - TM2 Continuous alternating pulses are sent on the S/T-interface. • Command Abbr. Deactivation Request DR Reset RES Send Single Pulses TM1 Send Continuous TM2 Pulses Activation Request AR Activation Request ARL Loop Deactivation DC Confirmation Indication Abbr. ...
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S-Transceiver Enable / Disable The layer-1 part of the S-transceiver can be enabled/disabled with the two bits S_CONF0.DIS_TR and S_CONF2.DIS_TX. If DIS_TX=’1’ the transmit buffers are disabled. The receiver will monitor for incoming data in this configuration. By default ...
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Interrupt Structure S-Transceiver • S_STA 7 RINF 0 FECV 0 FSYN SQRR MSYN 7 MFEN 0 0 SQR1 SQR2 SQR3 0 SQR4 SQXR 7 0 MFEN 0 0 SQX1 SQX2 SQX3 0 SQX4 Figure 57 Interrupt ...
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Operational Description 3.1 Layer 1 Activation/Deactivation 3.1.1 Complete Activation Initiated by Exchange Figure 58 depicts the procedure if activation has been initiated by the exchange side (LT). • IOM -2 TE S/T-Reference Point INFO INFO 0 ...
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Complete Activation Initiated by TE Figure 59 depicts the procedure if activation has been initiated by the terminal side (TE). • IOM -2 TE S/T-Reference Point INFO INFO 0 TIM PU AR INFO 1 INFO 2 ...
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Complete Activation Initiated by NT Figure 60 depicts the procedure if activation has been initiated by the Q-SMINT I itself (e.g. after hook-off of a local analog phone). • IOM -2 TE S/T-Reference Point INFO 0 DC INFO 0 ...
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Complete Deactivation Figure 61 depicts the procedure if deactivation has been initiated. Deactivation of layer 1 is always initiated by the exchange. • IOM -2 TE S/T-Reference Point INFO 4 AI (AR) INFO 3 INFO 0 RSY INFO 0 ...
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Loop 2 Figure 62 depicts the procedure if loop 2 is closed and opened. • S/T-Reference Point IOM - INFO AR8/10 INFO 3 SBCX-X or IPAC-X Figure 62 Loop 2 Data Sheet NT µC ...
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Layer 1 Loopbacks Test loopbacks are specified by the national PTTs in order to facilitate the location of defect systems. Four different loopbacks are defined. The position of each loopback is illustrated in Figure 63. • ® IOM -2 ...
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In order to open an analog loopback correctly, force the U-transceiver into the RESET state. This ensures that the echo coefficients and equalizer coefficients will converge correctly when activating anew. 3.2.2 Analog Loop-Back S-Transceiver The Q-SMINT I provides test and ...
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Loopback No.2 For loopback #2 several alternatives exist. Both the type of loopback and the location may vary. The following loopback types belong to the loopback-#2 category: • complete loopback (B1,B2,D), in the U-transceiver • complete loopback (B1,B2,D), in ...
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Loopback No.2 - Single Channel Loopbacks Single channel loopbacks are always performed directly in the U-Transceiver. No difference between the B1-channel and the B2-channel loopback control procedure exists. 3.2.4 Local Loopbacks Featured By the LOOP Register Besides the standardized ...
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LOOP.LB1=1 LOOP.LB2=1 LOOP.LBBD= 1 LOOP.U/IOM= Analog Part Digital Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter Timing Recovery U-Transceiver Bandgap, Bias, Refer. Digital Part Analog Part Line Interface Unit DAC Echo Canceller PDM + ADC Filter ...
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External Circuitry 3.3.1 Power Supply Blocking Recommendation The following blocking circuitry is suggested. • VDDa_UR VDDa_UX VDDa_SR VDDa_SX VDDD VDDD 1) 100nF VSSD VSSD VSSa_SX VSSa_SR VSSa_UX VSSa_UR 1) These capacitors should be located as near to the pins ...
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AOUT BIN AIN BOUT Figure 68 External Circuitry U-Transceiver U-Transformer Parameters The following Table 31 lists parameters of typical U-transformers: Table 31 U-Transformer Parameters U-Transformer Parameters U-Transformer ratio; Device side : Line side Main inductance of windings on the ...
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Resistors of the External Hybrid R3, R4 and 1 1 9.5 T Resistors on the Line Side R Optional use 2x20 requires compensation resistors ...
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Transformer Parameters Coupling capacitance between the windings on the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side Transmitter The transmitter requires external resistors ...
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Receiver The receiver of the S-transceiver is symmetrical recommended in each receive path preferable to split the resistance into two resistors for each line. This allows to place a high resistance between the transformer and the ...
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Table 33 Crystal Parameters Parameter Frequency Frequency calibration tolerance Load capacitance Max. resonance resistance Max. shunt capacitance Oscillator mode External Components and Parasitics The load capacitance C L capacitances C (pin and PCB capacitances to ground and V Par capacitance ...
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Register Description 4.1 Address Space Figure 72 Address Space Data Sheet 7D H U-Transceiver 60 H Monitor Handler 5C H IOM -2 Handler (CDA, TSDP, CR, STI Interrupt, Global Registers 3C H S-Transceiver 30 H CI-Register 2E ...
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Interrupts Special events in the Q-SMINT I are indicated by means of a single interrupt output, which requests the host to read status information from the Q-SMINT I or transfer data from/to the Q-SMINT I. Since only one INT ...
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After the Q-SMINT I has requested an interrupt by setting its INT pin to low, the host must read first the Q-SMINT I interrupt status register (ISTA) in the associated interrupt service routine. The INT pin of the Q-SMINT I ...
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Register Summary r(0) = reserved, implemented as zero. CI Handler Name 7 6 MODEH 1 1 CIR0 CODR0 CIX0 CODX0 CIR1 CIX1 Data Sheet reserved 0 r(0) 0 DIM2 reserved CIC0 CIC1 TBA2 TBA1 CODR1 ...
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S-Transceiver Name DIS_ BUS CONF0 TR S_ DIS_ 0 CONF2 TX S_STA RINF S_CMD XINF SQRR MSYN MFEN SQXR 0 MFEN ISTAS 0 x MASKS MODE Data Sheet ...
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Interrupt, General Configuration Name 7 6 ISTA U ST MASK U ST MODE1 MCLK CDS MODE2 LED2 LED1 LEDC SRES 0 0 RES_ CI/TIC Data Sheet CIC 0 WOV S CIC 1 WOV ...
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IOM Handler (Timeslot, Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 CDA11 CDA20 CDA21 CDA_ DPS 0 TSDP10 CDA_ DPS 0 TSDP11 CDA_ DPS 0 TSDP20 CDA_ DPS 0 TSDP21 S_ DPS 0 TSDP_ B1 ...
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IOM Handler (Control Registers, Synchronous Transfer Interrupt Control) Name 7 6 S_CR 1 CI_CS CI_CR DPS_ EN_ CI1 CI1 MON_ DPS EN_ CR MON SDS1_ ENS_ ENS_ CR TSS TSS+1 SDS2_ ENS_ ENS_ CR TSS TSS+1 IOM_CR SPU 0 MCDA ...
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MONITOR Handler Name 7 6 MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Data Sheet MONITOR Receive Data MONITOR Transmit Data MDA MAB 0 0 MIE MXC ...
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Register Summary U-Transceiver Name 7 6 OPMODE 0 UCI MFILT M56 FILTER EOCR EOCW M4RMASK M4WMASK M4R verified M4 bit data of last received superframe M4W M4 bit data to be send ...
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ISTAU MLT CI MASKU MLT CI FW_ VERSION *) read back function for test use Note: Registers, which are denoted as ‘reserved‘, may not be accessed by the µC, neither for read nor for write operations. 4.4 Reset of U-Transceiver ...
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U-Transceiver Mode Register Evaluation Timing The point of time when mode settings are detected and executed differs with the mode register type. Two different behaviors can be classified: • evaluation and execution after SW-reset (C/I= RES) or upon transition ...
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Detailed C/I Registers 4.6.1 MODEH - Mode Register IOM-2 MODEH Value after reset DIM2-0 Digital Interface Modes These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit enables/disables the ...
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CODR0 C/I0 Code Receive Value of the received Command/Indication code. A C/I-code is loaded in CODR0 only after being the same in two consecutive IOM-frames and the previous code has been read from CIR0. CIC0 C/I0 Code Change 0 = ...
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CIX0 - Command/Indication Transmit 0 CIX0 Value after reset CODX0 CODX0 C/I0-Code Transmit Code to be transmitted in the C/I-channel 0. The code is only transmitted if the TIC bus is occupied, otherwise “1s” are transmitted. ...
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CIR1 - Command/Indication Receive 1 CIR1 Value after reset CODR1 C/I1-Code Receive CICW C/I-Channel Width Contains the read back value from CIX1 register (see below bit C/I1 channel width bit ...
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C/I1 channel width The C/I1 handler always reads and writes 6-bit values but if 4-bit is selected, the higher two bits are ignored for interrupt generation. However, in write direction the full CODX1 code is transmitted, ...
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ICV enabled. The receipt of at least one illegal code violation within one multi-frame according to ANSI T1.605 is indicated by the C/I indication ‘1011’ (CVR) in two consecutive IOM frames. L1SW Enable Layer 1 State Machine in ...
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S_STA - S-Transceiver Status Register S_ STA Value after reset RINF Important: This register is used only if the Layer 1 state machine of the device is disabled (S_CONF0:L1SW = 1) and implemented in software! With ...
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S_CMD - S-Transceiver Command Register S_ CMD Value after reset XINF Important: This register - except bit DPRIO - is writable only if the Layer 1 state machine of the device is disabled (S_CONF0.L1SW = 1) ...
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Analog loop is open 1 = Analog loop is closed internally or externally according to the EXLP bit in the S_CONF0 register 4.7.5 SQRR - S/Q-Channel Receive Register SQRR Value after reset MSYN MFEN MSYN ...
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MFEN Multiframe Enable Used to enable or disable the multiframe structure S/T multiframe is disabled 1 = S/T multiframe is enabled SQX1-4 Transmitted S/Q Bits Transmitted S bits in frames and 16 4.7.7 ISTAS - ...
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SQC S/Q-Channel Change 0 = inactive change in the received 4-bit Q-channel has been detected. The new code can be read from the SQRx bits of registers SQRR within the next multiframe SQRR register. SQW S/Q-Channel Writable ...
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S_MODE - S-Transceiver Mode S_ MODE Value after reset DCH_ D-Channel Inhibit INH 0 = inactive 1 = The S-transceiver blocks the access to the D-channel inverting the E-bits. MODE Mode ...
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Interrupt and General Configuration Registers 4.8.1 ISTA - Interrupt Status Register ISTA Value after reset U-Transceiver Interrupt 0 = inactive interrupt was generated by the U-transceiver. Read the ISTAU register. ...
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An interrupt was generated by the S-transceiver. Read the ISTAS register. MOS MONITOR Status 0 = inactive change in the MONITOR Status Register (MOSR) has occurred inactive Note: A read ...
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MODE1 - Mode1 Register MODE1 Value after reset MCLK MCLK Master Clock Frequency The Master Clock Frequency bits control the microcontroller clock output depending on MODE1.CDS = ’0’ or ’1’ (Table MODE1.CDS = ’0’ ...
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CFS Configuration Select 0 = The IOM “Deactivated State” of the U-transceiver and the S-transceiver included The IOM “Deactivated State” of the U-transceiver and the S-transceiver. RSS2, Reset Source Selection 2,1 RSS1 The Q-SMINT I reset sources can ...
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AMOD Address Mode Selects between direct and indirect register access of the parallel microcontroller interface Indirect address mode is selected. The address line A0 is used to select between address (A0 = ‘0’) and data (A0 = ‘1’) ...
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SRES - Software Reset Register SRES Value after reset RES_xx Reset_xx 0 = Deactivates the reset of the functional block Activates the reset of the functional block xx. The reset state ...
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XXX_TSDPxy - Time Slot and Data Port Selection for CHxy XXX_TSDPxy 7 DPS 0 Register Value after Reset CDA_TSDP10 00 H CDA_TSDP11 01 H CDA_TSDP20 80 H CDA_TSDP21 81 H reserved S_TSDP_B1 84 H S_TSDP_B2 85 H This register ...
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CDAx_CR - Control Register Controller Data Access CH1x CDAx_CR Register Value after Reset Register Address CDA1_CR 00 H CDA2_CR 00 H EN_TBM Enable TIC Bus Monitoring 0 = The TIC bus monitoring is disabled 1 = ...
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SWAP Swap Inputs 0 = The time slot and data port for the input of the CDAxy register is defined by its own TSDPxy register. The data port for the CDAxy input is vice versa to the output setting for ...
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The corresponding data path to the transceiver is enabled. EN_B1R Enable Transceiver B1 Receive Data (transmitter receives from IOM The corresponding data path to the transceiver is disabled 1 = The corresponding data path to the ...
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EN_CI1 Enable CI1 Handler 0 = CI1 data access is disabled 1 = CI1 data access is enabled Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM channel 1. 4.9.6 MON_CR - Control Register ...
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SDS1_CR - Control Register Serial Data Strobe 1 SDS1_CR Value after reset ENS_ ENS_ TSS TSS+1 This register is used to select position and length of the strobe signal 1. The length can be any combination ...
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SDS2_CR - Control Register Serial Data Strobe 2 SDS2_CR Value after reset ENS_ ENS_ TSS TSS+1 This register is used to select position and length of the strobe signal 2. The length can be any combination ...
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IOM_CR - Control Register IOM Data IOM_CR Value after reset SPU 0 SPU Software Power The DU line is normally used for transmitting data Setting this bit to ‘1’ will pull ...
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The IOM interface is enabled 1 = The IOM interface is disabled (FSC, DCL, clock outputs have high impedance; DU, DD data line inputs are switched off and outputs are high impedant) 4.9.10 MCDA - Monitoring CDA Bits ...
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Enabled STOV interrupts for a certain STIxy interrupt are generated when the STIxy has not been acknowledged in time via the ACKxy bit in the ASTI register. This must be one (for DPS = ‘0’) or zero (for DPS = ...
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For the MSTI register the following logical states are applied Interrupt is not masked 1 = Interrupt is masked STOVxy Mask Synchronous Transfer Overflow xy Mask bits for the corresponding STOVxy interrupt bits. STIxy Synchronous Transfer Interrupt xy ...
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MOSR - MONITOR Interrupt Status Register MOSR Value after reset MDR MER MDR MONITOR channel Data Received 0 = inactive 1 = MONITOR channel Data Received MER MONITOR channel End of Reception 0 = inactive 1 ...
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MRE MONITOR Receive Interrupt Enable 0 = MONITOR interrupt status MDR generation is masked MONITOR interrupt status MDR generation is enabled. MRC MR Bit Control Determines the value of the MR bit always ‘1’. ...
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MAC MONITOR Transmit Channel Active data transmission in the MONITOR channel 1 = The data transmission in the MONITOR channel is in progress. TOUT Time-Out Read-back value of the TOUT bit 0 = The monitor time-out function ...
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UCI Enable/Disable C Control of C/I Codes control disabled - C/I codes are exchanged via IOM Read access to register UCIR by the P is still possible control enabled - C/I codes are exchanged ...
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M56 FILTER M56 controls the validation mode of the spare bits (M51, M52, M61 per bit FILTER base (see Chapter X0 = Apply same filter to M5 and M6 bit data as programmed for M4 bit ...
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EOC Embedded Operations Channel (see address field d/m data/ message indicator information field, 4.11.4 EOCW - EOC Write Register Via the EOC Write register, the EOC ...
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ANSI/ETSI for diagnostic and loopback functions) 4.11.5 M4RMASK - M4 Read Mask Register Via the M4 Read Mask register, the user ...
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Bit 0.. bit is controlled by state machine/ external pins (PS1, bit is controlled by C Bit 6 Partial Activation Control External/Automatic, function corresponds to the MON-8 commands PACE and PACA 0 = SAI ...
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U-transceiver is operated within a DCL configuration as LULT it shall start operation as soon as power is applied DEA Deactivation Bit informs NT that it will turn off 1 = ...
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NTM NT Test Mode busy in test mode 1 = inactive PS2 Power Status Secondary Source 0 = secondary power supply failed 1 = secondary power supply ok PS1 Power Status Primary Source 0 = primary power ...