SC16IS740IPW,112 NXP Semiconductors, SC16IS740IPW,112 Datasheet - Page 29
![IC UART SINGLE W/FIFO 16-TSSOP](/photos/6/56/65607/568-16-tssop_sot403-1_sml.jpg)
SC16IS740IPW,112
Manufacturer Part Number
SC16IS740IPW,112
Description
IC UART SINGLE W/FIFO 16-TSSOP
Manufacturer
NXP Semiconductors
Type
UART with 64-byte FIFOs and IrDA encoder/decoderr
Datasheet
1.SC16IS740IPW112.pdf
(62 pages)
Specifications of SC16IS740IPW,112
Number Of Channels
1, UART
Package / Case
16-TSSOP (0.173", 4.40mm Width)
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V, 3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-3648-5
935280988112
SC16IS740IPW
935280988112
SC16IS740IPW
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16IS740IPW,112
Manufacturer:
JAMICON
Quantity:
101
NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
8.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, modem status, Xoff received, or CTS/RTS change of
state from LOW to HIGH. The IRQ output signal is activated in response to interrupt
generation.
Table 19.
[1]
[2]
Bit
7
6
5
4
3
2
1
0
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will not
cause a new interrupt if the THR is below the threshold.
Only available on the SC16IS750/SC16IS760.
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Table 19
[1]
[1]
[1]
[1]
Description
CTS interrupt enable
RTS interrupt enable
Xoff interrupt
Sleep mode
Modem Status Interrupt
Remark: See IOControl register bit 1 in
program the pins as modem pins.
Receive Line Status interrupt
Transmit Holding Register interrupt.
Receive Holding Register interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
shows the Interrupt Enable Register bit settings.
Single UART with I
Rev. 06 — 13 May 2008
[2]
.
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
Section 7.6 “Sleep mode”
Table 30
for the description of how to
© NXP B.V. 2008. All rights reserved.
for details.
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