PCF2123BS/1 NXP Semiconductors, PCF2123BS/1 Datasheet - Page 19

• Manufacturer Part Number: PCF2123BS/1
• Manufacturer: NXP Semiconductors

Specifications of PCF2123BS/1

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF2123
Product data sheet
The generation of interrupts from the alarm function is controlled via bit AIE (register
Control_2, see
will remain set until cleared by the interface. Once AF has been cleared, it will only be set
again when the time increments to match the alarm condition once more. Alarm registers
which have their AE_x bit logic 1 are ignored.
Generation of interrupts from the alarm function is described in
Figure
MSF and bit TF unaffected. The flags are cleared by a write command, therefore bits 7, 6,
4, 1 and 0 must be written with their previous values. Repeatedly re-writing these bits has
no influence on the functional behavior.
To prevent the timer flags being overwritten while clearing bit AF, logic AND is performed
during a write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by
writing logic 1. Writing logic 1 will result in the flag value remaining unchanged.
Table 22.
Table 23
bit TF are unaffected.
Table 23.
Register
Control_2
Register
Control_2
Fig 13. Alarm flag timing
13,
shows what instruction must be sent to clear bit AF. In this example, bit MSF and
Example where only the minute alarm is used and no other interrupts are enabled.
Table
Flag location in register Control_2
Example to clear only AF (bit 3) in register Control_2
Table
Bit
7
-
Bit
7
-
All information provided in this document is subject to legal disclaimers.
INT when AIE = 1
22, and
minutes counter
minute alarm
7). If bit AIE is enabled, the INT pin follows the condition of bit AF. AF
Rev. 5 — 27 April 2011
6
-
6
-
Table 23
AF
44
45
5
MSF
5
1
show an example for clearing bit AF, but leaving bit
4
-
4
-
45
3
AF
3
0
SPI Real time clock/calendar
2
TF
2
1
Section
001aaf903
46
PCF2123
© NXP B.V. 2011. All rights reserved.
1
-
1
-
8.7.3.
0
-
0
-
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