SC16C752BIBS,128 NXP Semiconductors, SC16C752BIBS,128 Datasheet - Page 19

• Manufacturer Part Number: SC16C752BIBS,128
• Description: IC DUAL UART 64BYTE 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C752BIBS,128

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276389128; SC16C752BIBS-F; SC16C752BIBS-F

NXP Semiconductors
7. Register descriptions
SC16C752B
Product data sheet
Each register is selected using address lines A0, A1, A2, and in some cases, bits from
other registers. The programming combinations for register selection are shown in
Table
Table 9.
[1]
[2]
[3]
[4]
[5]
[6]
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
Fig 13. Crystal oscillator connections
MCR[7] can only be modified when EFR[4] is set.
Accessed by a combination of address pins and register bits.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 1011 1111 (BFh).
Accessible only when EFR[4] = logic 1 and MCR[6] = logic 1, i.e., EFR[4] and MCR[6] are read/write
enables.
Accessible only when CSA or CSB = logic 0, MCR[2] = logic 1, and loopback is disabled
(MCR[4] = logic 0).
9.
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
Register map - read/write properties
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
All information provided in this document is subject to legal disclaimers.
Read mode
Receive Holding Register (RHR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
Scratchpad Register (SPR)
Divisor Latch LSB (DLL)
Divisor Latch MSB (DLM)
Enhanced Feature Register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register (TCR)
Trigger Level Register (TLR)
FIFO ready register
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 6 — 30 November 2010
XTAL1
1.8432 MHz
C1
22 pF
[2][4]
[2][4]
[2][4]
[2][4]
X1
XTAL2
[2][6]
C2
33 pF
[2][3]
[2][3]
[2][5]
[1]
[2][4]
XTAL1
[2][5]
1.8432 MHz
C1
22 pF
X1
Write mode
Transmit Holding Register (THR)
Interrupt Enable Register
FIFO Control Register (FCR)
Line Control Register
Modem Control Register
Scratchpad Register
Divisor Latch LSB
Divisor Latch MSB
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmission Control Register
Trigger Level Register
XTAL2
002aaa870
1.5 kΩ
C2
47 pF
SC16C752B
[2][4]
[2][4]
[2][4]
[2][4]
© NXP B.V. 2010. All rights reserved.
[2][3]
[2][3]
[2][5]
[1]
[2][4]
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[2][5]