SC16C752BIBS,128 NXP Semiconductors, SC16C752BIBS,128 Datasheet - Page 22

• Manufacturer Part Number: SC16C752BIBS,128
• Description: IC DUAL UART 64BYTE 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C752BIBS,128

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276389128; SC16C752BIBS-F; SC16C752BIBS-F

NXP Semiconductors
SC16C752B
Product data sheet
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling.
shows FIFO control register bit settings.
Table 11.
Bit
7:6
5:4
3
2
1
0
Symbol
FCR[7] (MSB),
FCR[6] (LSB)
FCR[5] (MSB),
FCR[4] (LSB)
FCR[3]
FCR[2]
FCR[1]
FCR[0]
FIFO Control Register bits description
All information provided in this document is subject to legal disclaimers.
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
DMA mode select.
Rev. 6 — 30 November 2010
Description
RX trigger. Sets the trigger level for the receive FIFO.
TX trigger. Sets the trigger level for the transmit FIFO.
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
Reset transmit FIFO.
Reset receive FIFO.
FIFO enable.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO.
SC16C752B
© NXP B.V. 2010. All rights reserved.
Table 11
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