SC16C752BIBS,151 NXP Semiconductors, SC16C752BIBS,151 Datasheet - Page 20

• Manufacturer Part Number: SC16C752BIBS,151
• Description: IC UART DUAL W/FIFO 32-HVQFN
• Manufacturer: NXP Semiconductors
• Type: Dual UART with 64-byte FIFOsr

Specifications of SC16C752BIBS,151

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: False-start Bit Detection
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3288; 935276389151; SC16C752BIBS-S

NXP Semiconductors
Table 10.
[1]
[2]
[3]
[4]
SC16C752B
Product data sheet
A2 A1 A0 Register Bit 7
General register set
0
0
0
0
0
0
1
1
1
1
1
1
1
Special register set
0
0
Enhanced register set
0
1
1
1
1
These registers are accessible only when LCR[7] = logic 0.
These bits can only be modified if register bit EFR[4] is enabled, i.e., if enhanced functions are enabled.
The Special register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to BFh.
0
0
0
1
1
1
0
0
1
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
SC16C752B internal registers
RHR
THR
IER
FCR
IIR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
FIFO
Rdy
DLL
DLM
EFR
Xon1
Xon2
Xoff1
Xoff2
[3]
[1]
[4]
bit 7
0/CTS
interrupt
enable
RX trigger
level
(MSB)
FCR[0]
DLAB
1× or
1× / 4
clock
0/error in
RX FIFO
CD
bit 7
0
bit 7
bit 15
auto CTS auto RTS
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
bit 7
Table 10
[2]
[2]
lists and describes the SC16C752B internal registers.
Bit 6
bit 6
bit 6
0/RTS
interrupt
enable
RX trigger
level (LSB)
FCR[0]
break
control bit
TCR and
TLR
enable
THR and
TSR empty
RI
bit 6
bit 6
bit 6
0
bit 6
bit 14
bit 6
bit 6
bit 6
bit 6
All information provided in this document is subject to legal disclaimers.
[2]
[2]
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Rev. 6 — 30 November 2010
Bit 5
bit 5
bit 5
0/Xoff
0/TX
trigger
level
(MSB)
0/CTS,
RTS
set parity
0/Xon
Any
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
Special
character
detect
bit 5
bit 5
bit 5
bit 5
[2]
[2]
[2]
Bit 4
bit 4
bit 4
0/X sleep
mode
0/TX
trigger
level
(LSB)
0/Xoff
parity type
select
0/enable
loopback
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
Enable
IER[7:4],
FCR[5:4],
MCR[7:5]
bit 4
bit 4
bit 4
bit 4
[2]
[2]
bit 3
interrupt
Bit 3
bit 3
modem
status
interrupt
DMA
mode
select
priority
bit 2
parity
enable
IRQ
enable
OP
framing
error
ΔCD
bit 3
bit 3
bit 3
0
bit 3
bit 11
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
interrupt
priority
bit 1
number of
stop bits
FIFO
ready
enable
parity
error
ΔRI
bit 2
bit 2
bit 2
0
bit 2
bit 10
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
bit 1
Bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
interrupt
priority
bit 0
word
length
bit 1
RTS
overrun
error
ΔDSR
bit 1
bit 1
bit 1
TX FIFO
B status
bit 1
bit 9
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
SC16C752B
© NXP B.V. 2010. All rights reserved.
Bit 0
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
interrupt
status
word
length
bit 0
DTR
data in
receiver
ΔCTS
bit 0
bit 0
bit 0
TX FIFO
A status
bit 0
bit 8
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
20 of 47
Read/
Write
R
W
R/W
W
R
R/W
R/W
R
R
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W