CY7C4291-15JXCT Cypress Semiconductor Corp, CY7C4291-15JXCT Datasheet - Page 5

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CY7C4291-15JXCT

Manufacturer Part Number
CY7C4291-15JXCT
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4291-15JXCT

Lead Free Status / Rohs Status
Compliant
Document #: 38-06007 Rev. *C
WRITE ENABLE 1(WEN1)
WRITE ENABLE 2/LOAD
PROGRAMMABLE(PAF)
DATA IN (D)
WRITECLOCK (WCLK)
Figure 2. Block Diagram of 64k x 9/128k x 9 Deep Sync FIFO Memory Used in a Width Expansion Configuration
FULL FLAG (FF) # 1
FULL FLAG (FF) # 2
(WEN2/LD)
18
9
Read Enable 2 (REN2)
FF
CY7C4281/91
RESET (RS)
EF
9
9
Read Enable 2 (REN2)
FF
CY7C4281/91
RESET (RS)
EF
EMPTY FLAG (EF) #2
EMPTY FLAG (EF) #1
9
READ CLOCK (RCLK)
READ ENABLE 1 (REN1)
OUTPUT ENABLE (OE)
PROGRAMMABLE(PAE)
DATA OUT (Q)
CY7C4281
CY7C4291
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